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| HT83F02 external voice memory flash mcu rev. 1.20 1 november 19, 2010 general description the flash type voice of mcu has flash type program memory and connect external flash through spi serial interface. offering users the convenience of flash memory multi-programming features, this device also includes a wide range of functions and features which include a voice synthesizer and tone generator. this device is designed for applications which require multiple i/os and sound effects, such as voice and mel- ody. it can provide various sampling rates and beats, tone levels, tempos for speech synthesizer and melody generator. it also includes two integrated high quality, voltage type dac outputs and voltage type pwm out- puts. this device is excellent solutions for versatile voice and sound effect product applications with their efficient mcu instructions providing the user with programming capability for powerful custom applications. the system frequency can be up to 12mhz at an operating voltage of 5v and include a power-down function to reduce power consumption. a full choice of hxt, erc and hirc oscillator functions are provided including a fully integrated system oscillator which requires no external components for its implementation. the mcu flash voice memory capacity determine by user, into which the user can download their voice data. features operating voltage: 2.4v~5.5v system clock: 4mhz~12mhz three oscillators: external crystal - hxt external rc - erc internal rc - hirc fully integrated internal 4mhz, 8mhz and 12mhz oscillator requires no external components up to 19 i/o pins two sets of serial interfaces module - sim for spi or i 2 c, shared with pb 2k 16 flash program memory 208 8 data memory two 8-bit programmable timer counter with 8-stage prescaler and one time base counter 12-bit high quality voltage type d/a output pwm circuit direct drive speaker watchdog timer function 8-level subroutine nesting 2.7v low voltage detection, tolerance 5% 2.4v low voltage reset, tolerance 5% power-down function and wake-up feature reduce power consumption 63 powerful instructions 28-pin ssop package
block diagram the following block diagram illustrates the main functional blocks. pin assignment HT83F02 rev. 1.20 2 november 19, 2010 ! " # $ $ " % ! & " % ! $ $ ' ( ) * + ! , $ ! ! - . / 0 1 0 1 1 1 / 2 1 ) 1 1 # 1 1 3 1 4 2 ) 1 5 1 6 / / # # + & + # 7 3 4 5 6 + + + 8 1 0 ( + " # " / + # # 6 # 5 # 4 # 3 # 7 # # # / # 0 / 9 / / 6 / 5 / 4 / # 7 3 4 5 6 9 / 0 / / / # / 7 / 3 pin description pin name i/o options description pa0~pa7 i/o wake-up, pull-high or none bidirectional 8-bit i/o port, each bit can be configured as a wake-up input by configuration option. software instructions determine if the pin is a cmos out - put or schmitt trigger input. configuration options determine which pins on this port have pull-high resistors. pb0/sdob/sdab pb1/sckb/sclb pb2/sdib pb3/scsb pb4/sdoa/sdaa pb5/scka/scla pb6/sdia pb7/scsa i/o pull-high or none bidirectional 8-bit i/o port. software instructions determine if the pin is a cmos output or schmitt trigger input. configuration options determine which pins on this port have pull-high resistors. pins pb0~pb3 are pin-shared with simb control pins sdob/sdab, sckb/sclb, sdib and scsb respectively. pins pb4~pb7 are pin-shared with sima control pins sdoa/sdaa, scka/scla, sdia and scsa respectively. vss negative digital power supply, ground vdd positive digital power supply vdd_pbio pb i/o external positive power supply(determine by option) pc0/res i schmitt trigger reset input or pc0 i/o pin. configuration option determines if the pin is as a reset pin or gpio pin. software instructions determine if this pin has pull-high resistor. pc1/osc1 pc2/osc2 crystal, erc or irc osc1, osc2 are connected to an external rc network, external crystal or no connection, determined by configuration option, for the internal system clock. if the erc system clock option is selected, pin osc2 can be as pc2. if the irc system clock option is selected, the osc1/osc2 pins will be io pins pc1/pc2. software instructions determine which pins on this port have pull-high resistors. vssa negative dac circuit power supply, ground aud o cmos audio output for driving external transistor or power amplifier. vdda positive dac circuit power supply vddp pwm positive power supply pwm1, pwm2 o pwm circuit direct speaker drive vssp pwm negative power supply, ground note: each pin on pa can be programmed through a configuration option to have a wake-up function. individual pins can be selected to have pull-high resistors. absolute maximum ratings supply voltage ...........................v ss +2.4v to v ss +5.5v storage temperature .......................... 50 c to +125c input voltage..............................v ss 0.3v to v dd +0.3v operating temperature......................... 40 cto+85 c i ol total ..............................................................150ma i oh total............................................................ 100ma total power dissipation .....................................500mw note: these are stress ratings only. stresses exceeding the range specified under absolute maximum ratings may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. HT83F02 rev. 1.20 3 november 19, 2010 d.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions v dd1 operating voltage (crystal osc) f sys =8mhz 2.4 5.5 v f sys =10mhz 2.7 5.5 v f sys =12mhz 3.3 5.5 v v dd2 operating voltage (external rc osc) f sys =6mhz 2.4 5.5 v f sys =8mhz 2.7 5.5 v f sys =12mhz 2.7 5.5 v v dd3 operating voltage (high frequency internal rc osc) f sys =8mhz 2.4 5.5 v f sys =12mhz 2.7 5.5 v i dd1 operating current (crystal osc, f sys =f h ) 3v no load, f h =8mhz, wdt enable 0.8 1.5 ma 5v 2.5 4.0 ma 3v no load, f h =10mhz, wdt enable 1.0 2.0 ma 5v 2.3 4.5 ma 3v no load, f h =12mhz, wdt enable 1.1 2.5 ma 5v 2.7 5.5 ma i dd2 operating current (erc osc, f sys =f h ) 3v no load, f h =6mhz, wdt enable 0.7 1.5 ma 5v 1.7 3.0 ma 3v no load, f h =8mhz, wdt enable 1.0 2.0 ma 5v 2.1 4.5 ma 3v no load, f h =12mhz, wdt enable 1.4 3.0 ma 5v 3.1 6.0 ma i dd3 operating current (hirc osc, f sys =f h ) 3v no load, f h =4mhz, wdt enable 0.5 1.2 ma 5v 1.2 2.5 ma 3v no load, f h =8mhz, wdt enable 1.1 2.0 ma 5v 2.2 4.5 ma 3v no load, f h =12mhz, wdt enable 1.4 3.0 ma 5v 3.2 6.0 ma i stb1 standby current (crystal, erc, hirc osc) 3v no load, system halt, wdt enable, f sys =12mhz 1.1 5.0 a 5v 4.1 10.0 a i stb2 standby current (crystal, erc, hirc osc) 3v no load, system halt, wdt disable, f sys =12mhz 0.2 1.0 a 5v 0.4 2.0 a i ol1 i/o port sink current 3v v ol =0.1v dd 713 ma 5v 15 30 ma i oh1 i/o port source current 3v v oh =0.9v dd 3.5 5 ma 5v 8.0 12 ma i ol2 pwm1/pwm2 sink current 3v v ol =0.1v dd 70 100 ma 5v 125 180 ma HT83F02 rev. 1.20 4 november 19, 2010 symbol parameter test conditions min. typ. max. unit v dd conditions i oh2 pwm1/pwm2 sink current 3v v oh =0.9v dd 38 55 ma 5v 80 115 ma v il1 input low voltage for pa i/o ports 3v 1.0 v 5v 2.0 v v ih1 input high voltage for pa i/o ports 3v 1.9 v 5v 3.0 v v il2 input low voltage (res ) 3v 1.4 v 5v 2.8 v v ih2 input high voltage (res ) 3v 2.1 v 5v 3.7 v v il3 input low voltage for pb i/o ports (pbvdd=vdd) 3v 1.1 v 5v 2.2 v v ih3 input high voltage for pb i/o ports (pbvdd=vdd) 3v 1.9 v 5v 3.0 v v il4 input low voltage for pb i/o ports (pbvdd=vdd_pbio) 3v 1.3 v 5v 2.5 v v ih4 input low voltage for pb i/o ports (pbvdd=vdd_pbio) 3v 1.6 v 5v 2.6 v r ph pull-high resistance 3v 20 60 100 k 5v 10 30 50 k i aud aud current source 3v v oh =0.9v dd 4.5 ma 5v v oh =0.9v dd 10.5 ma v lvr low voltage reset voltage lvr 2.4v option 2.28 2.40 2.52 v v lvd low voltage detection voltage lvr 2.7v option 2.565 2.700 2.835 v HT83F02 rev. 1.20 5 november 19, 2010 a.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions f sys1 system clock (crystal osc) 2.4v~ 5.5v 2 8 mhz 2.7v~ 5.5v 2 10 mhz 3.3v~ 5.5v 2 12 mhz f sys2 system clock (external rc osc) 5v ta=25c, external r erc =120k -2% typ. 8 2% typ. mhz f sys3 system clock (hi rc osc) 3v/5v ta=25c -2% typ. 8 2% typ. mhz t res external reset low pulse width 1 s t sst system start-up timer period (wake-up from halt) f sys =xtal 1024 t sys f sys =erc or hirc osc 15~16 t sys 1 t sys t int interrupt pulse width 7 8 s t lvr low voltage width to reset 320 840 1200 s t lvd lvd time 15 s note: t sys =1/f sys t sub =1/f sub HT83F02 rev. 1.20 6 november 19, 2010 power-on reset characteristics symbol parameter test conditions min. typ. max. unit v dd conditions v por vdd start voltage to ensure power-on reset 100 mv rr vdd vdd raising rate to ensure power-on reset 0.035 v/ms t por minimum time for vdd stays at v por to ensure power-on reset 1 ms characteristics curves r vs. f (external rc) chart characteristics curve at 25 c HT83F02 rev. 1.20 7 november 19, 2010 + + + : $ - , ; . # / 0 0 / # 0 / 4 9 # 3 0 # 3 5 / 0 / # / 3 + < 7 = 7 + - . t vs. f (external rc) chart characteristics curve v vs. f (hirc) chart characteristics curve at 25 c trimmed at 5v HT83F02 rev. 1.20 8 november 19, 2010 : $ - , ; . # 3 5 / 0 / # , ; + - + . 3 , ; / # , ; # = 4 7 = 0 7 = 4 3 = 0 4 = 0 5 = 0 3 = 4 4 = 4 / 3 / 5 9 0 # 4 3 4 0 = 9 0 = 9 9 / = 0 0 / = 0 / / = 0 # / = 0 7 , ; > + < 7 = 7 + - . ? ? - # 4 . v vs. f (hirc) chart characteristics curve at 25 c trimmed at 3v HT83F02 rev. 1.20 9 november 19, 2010 : $ - , ; . # 3 5 / 0 / # , ; + - + . 3 , ; / # , ; # = 4 7 = 0 7 = 4 3 = 0 4 = 0 5 = 0 3 = 4 4 = 4 / 3 / 5 HT83F02 rev. 1.20 10 november 19, 2010 system architecture a key factor in the high-performance features of the holtek range of microcontrollers is attributed to the inter - nal system architecture. the range of devices take ad - vantage of the usual features found within risc microcontrollers providing increased speed of operation and enhanced performance. the pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or call instructions. an 8-bit wide alu is used in practically all operations of the instruction set. it car - ries out arithmetic operations, logic operations, rotation, increment, decrement, branch decisions, etc. the inter - nal data path is simplified by moving data through the accumulator and the alu. certain internal registers are implemented in the data memory and can be directly or indirectly addressed. the simple addressing methods of these registers along with additional architectural fea - tures ensure that a minimum of external components is required to provide a functional i/o control system with maximum reliability and flexibility. clocking and pipelining the main system clock, derived from either a crystal, erc or irc oscillator, is subdivided into four internally generated non-overlapping clocks, t1~t4. the pro - gram counter is incremented at the beginning of the t1 clock during which time a new instruction is fetched. the remaining t2~t4 clocks carry out the decoding and ex - ecution functions. in this way, one t1~t4 clock cycle forms one instruction cycle. although the fetching and execution of instructions takes place in consecutive in - struction cycles, the pipelining structure of the microcontroller ensures that instructions are effectively executed in one instruction cycle. the exception to this are instructions where the contents of the program counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute. for instructions involving branches, such as jump or call instructions, two machine cycles are required to com - plete instruction execution. an extra cycle is required as the program takes one cycle to first obtain the actual jump or call address and then another cycle to actually execute the branch. the requirement for this extra cycle should be taken into account by programmers in timing sensitive applications. = - . ( @ $ = - / . = - a / . ( @ $ = - . = - a # . ( @ $ = - a / . a / a # - . / ! $ # 7 3 ' ! system clocking and pipelining = / ( @ $ = / = # $ ' / # 7 3 4 5 ( ) b c + > d / # , e ) ) ( ) b ) d / # , e c c f ( @ $ = # = 7 = 5 ( @ $ = 5 = 6 instruction fetching HT83F02 rev. 1.20 11 november 19, 2010 program counter during program execution, the program counter is used to keep track of the address of the next instruction to be executed. it is automatically incremented by one each time an instruction is executed except for instructions, such as jmp or call , that demand a jump to a non-consecutive program memory address. note that the program counter width varies with the program memory capacity depending upon which device is se - lected. however, it must be noted that only the lower 8 bits, known as the program counter low register, are directly addressable by user. when executing instructions requiring jumps to non-consecutive addresses such as a jump instruction, a subroutine call, interrupt or reset, etc., the microcontroller manages program control by loading the required address into the program counter. for condi - tional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execution, is dis - carded and a dummy cycle takes its place while the cor - rect instruction is obtained. the lower byte of the program counter, known as the program counter low register or pcl, is available for program control and is a readable and writable register. by transferring data directly into this register, a short program jump can be executed directly, however, as only this low byte is available for manipulation, the jumps are limited to the present page of memory, that is 256 locations. when such program jumps are executed it should also be noted that a dummy cycle will be in- serted. the lower byte of the program counter is fully accessi- ble under program control. manipulating the pcl might cause program branching, so an extra cycle is needed to pre-fetch. further information on the pcl register can be found in the special function register section. stack this is a special part of the memory which is used to save the contents of the program counter only. the stack has 8 levels and is neither part of the data nor part of the program space, and can neither be read from nor written to. the activated level is indexed by the stack pointer, sp, which can also neither be read from nor written to. at a subroutine call or interrupt acknowledge signal, the contents of the program counter are pushed onto the stack. at the end of a subroutine or an interrupt routine, signaled by a return instruction, ret or reti , the program counter is restored to its previous value from the stack. after a device reset, the stack pointer will point to the top of the stack. if the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded but the ac- knowledge signal will be inhibited. when the stack pointer is decremented, by ret or reti, the interrupt will be serviced. this feature prevents stack overflow al- lowing the programmer to use the structure more easily. mode program counter *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0 initial reset 00000000000 timer base overflow 00000000100 timer counter 0 overflow 00000001000 timer counter 1 overflow 00000001100 sima interrupt 00000010000 simb interrupt 00000010100 skip program counter + 2 loading pcl *10 *9 *8 @7 @6 @5 @4 @3 @2 @1 @0 jump, call branch #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0 return from subroutine s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 s0 program counter note: *10~*0: program counter bits s10~s0: stack register bits #10~#0: instruction code bits @7~@0: pcl bits ! $ ) / ) # ) 7 ) ! ' ? 1 ? HT83F02 rev. 1.20 12 november 19, 2010 however, when the stack is full, a call subroutine in - struction can still be executed which will result in a stack overflow. precautions should be taken to avoid such cases, which might cause unpredictable program branching. arithmetic and logic unit alu the arithmetic-logic unit or alu is a critical area of the microcontroller that carries out arithmetic and logic op - erations of the instruction set. connected to the main microcontroller data bus, the alu receives related in - struction codes and performs the required arithmetic or logical operations after which the result will be placed in the specified register. as these alu calculation or oper - ations may result in carry, borrow or other status changes, the status register will be correspondingly up - dated to reflect these changes. the alu supports the following functions: arithmetic operations add, addm, adc, adcm, sub, subm, sbc, sbcm, daa logic operations and, or, xor, andm, orm, xorm, cpl, cpla rotation rra, rr, rrca, rrc, rla, rl, rlca, rlc increment and decrement inca, inc, deca, dec branch decision jmp, sz, sza, snz, siz, sdz, siza, sdza, call, ret, reti flash program memory the program memory is the location where the user code or program is stored. for this device series the program memory is flash type, which means it can be programmed and re-programmed a large number of times, allowing the user the convenience of code modifi - cation on the same device. by using the appropriate programming tools, this flash device offers users the flexibility to conveniently debug and develop their appli - cations while also offering a means of field programming and updating. structure the program memory has a capacity of 2k by 16 bits. the program memory is addressed by the program counter and also contains data, table information and interrupt entries. table data, which can be setup in any location within the program memory, is addressed by separate table pointer registers. special vectors within the program memory, certain locations are re - served for special usage such as reset and interrupts. location 000h this vector is reserved for use by the device reset for program initialisation. after a device reset is initiated, the program will jump to this location and begin execution. location 004h this vector is used by the external interrupt. if the ex - ternal interrupt pin on the device goes low, the pro - gram will jump to this location and begin execution if the external interrupt is enabled and the stack is not full. location 008h this vector is used by the 8-bit timer 0. if a overflow occurs, the program will jump to this location and be - gin execution if the timer interrupt is enabled and the stack is not full. location 00ch this vector is used by the 8-bit timer1. if a overflow occurs, the program will jump to this location and be - gin execution if the timer interrupt is enabled and the stack is not full. location 010h this vector is used by the sima bus interrupt service program. if the sima bus interrupt resulting from a slave address is matched or if 8 bits of data have been received or transmitted successfully from the i 2 c inter - face, or 8 bits of data have been received or transmit - ted successful from spi interface, the program will jump to this location and begin execution if the inter- rupt is enabled and the stack is not full. location 014h this vector is used by the simb bus interrupt service program. if the simb bus interrupt resulting from a slave address is matched or if 8 bits of data have been received or transmitted successfully from the i 2 c inter- face, or 8 bits of data have been received or transmit- ted successful from spi interface, the program will jump to this location and begin execution if the inter - rupt is enabled and the stack is not full. 6 , / 5 0 / 4 , 0 0 0 , 0 0 3 , 0 0 , 0 0 , 0 / 0 , + 1 $ ' + $ 0 $ ' + 0 / 3 , $ / $ ' + 1 $ ' + $ ' + program memory structure HT83F02 rev. 1.20 13 november 19, 2010 look-up table any location within the program memory can be defined as a look-up table where programmers can store fixed data. to use the look-up table, table pointers are used to setup the address of the data that is to be accessed from the program memory. however, as some devices pos - sess only a low byte table pointer and other devices pos - sess both a high and low byte pointer it should be noted that depending upon which device is used, accessing look-up table data is implemented in slightly different ways. there are two table pointer registers known as tblp and tbhp in which the lower order and higher order ad - dress of the look-up data to be retrieved must be respec - tively first written. the additional tbhp register allows the complete address of the look-up table to be defined and consequently allow table data from any address and any page to be directly accessed. for this device, after setting up both the low and high byte table pointers, the table data can then be retrieved from any area of program memory using the tabrdc [m] instruction or from the last page of the program memory using the tabrdl [m] instruction. when either of these instruc - tions are executed, the lower order table byte from the program memory will be transferred to the user defined data memory register [m] as specified in the instruction. the higher order table data byte from the program memory will be transferred to the tblh special register. any unused bits in this transferred higher order byte will be read as 0. the following diagram illustrates the addressing/data flow of the look-up table. table program example the following example shows how the table pointer and table data is defined and retrieved from the devices. this example uses raw table data located in the last page which is stored there using the org statement. the value at this org statement is 700h which refers to the start address of the last page within the 2048 16-bit program memory of the microcontroller. the table pointer is setup here to have an initial value of 06h . this will ensure that the first data read from the data table will be at the program memory address 706h or 6 locations after the start of the last page. note that the value for the table pointer is referenced to the first address of the present page if the tabrdc[m] instruction is being used. the high byte of the table data which in this case is equal to zero will be transferred to the tblh register automatically when the tabrdl [m] instruction is executed. ! 1 ) , ' ? % d e , ! 1 ? ) * 1 ? 1 ) ! $ , ! 1 look-up table tempreg1 db ? ; temporary register #1 tempreg2 db ? ; temporary register #2 : : mov a,06h ; initialise table pointer - note that this address is referenced mov tblp,a ; to the last page or present page : : tabrdl tempreg1 ; transfers value in table referenced by table pointer ; to tempregl ; data at prog. memory address 706h transferred to ; tempreg1 and tblh dec tblp ; reduce value of table pointer by one tabrdl tempreg2 ; transfers value in table referenced by table pointer ; to tempreg2 ; data at prog.memory address 705h transferred to ; tempreg2 and tblh ; in this example the data 1ah is transferred to ; tempreg1 and data 0fh to register tempreg2 ; the value 00h will be transferred to the high byte ; register tblh : : org 700h ; sets initial address of HT83F02 last page dc 00ah, 00bh, 00ch, 00dh, 00eh, 00fh, 01ah, 01bh : : HT83F02 rev. 1.20 14 november 19, 2010 because the tblh register is a read-only register and cannot be restored, care should be taken to ensure its protection if both the main routine and interrupt service routine use table read instructions. if using the table read instructions, the interrupt service routines may change the value of the tblh and subsequently cause errors if used again by the main routine. as a rule it is recommended that simultaneous use of the table read instructions should be avoided. however, in situations where simultaneous use cannot be avoided, the inter - rupts should be disabled prior to the execution of any main routine table-read instructions. note that all table related instructions require two instruction cycles to complete their operation. instruction table location *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0 tabrdc [m] p10 p9 p8 @7 @6 @5 @4 @3 @2 @1 @0 tabrdl [m] 1 1 1 @7 @6 @5 @4 @3 @2 @1 @0 table location note: *10~*0: current program rom table p10~p8: write p12~p8 to tbhp pointer register @7~@0: write @7~@0 to tblp pointer register in circuit programming the provision of flash type program memory provides the user with a means of convenient and easy upgrades and modifications to their programs on the same device. as an additional convenience, holtek has provided a means of programming the microcontroller in-circuit us - ing a 5-pin interface. this provides manufacturers with the possibility of manufacturing their circuit boards com- plete with a programmed or un-programmed microcontroller, and then programming or upgrading the program at a later stage. this enables product manufac- turers to easily keep their manufactured products sup- plied with the latest program releases without removal and re-insertion of the device. mcu programming pins function pa0 serial data input/output pa2 serial clock res device reset vdd power supply vss ground the program memory can be programmed serially in-circuit using this 5-wire interface. data is downloaded and uploaded serially on a single pin with an additional line for the clock. two additional lines are required for the power supply and one line for the reset. the techni - cal details regarding the in-circuit programming of the devices are beyond the scope of this document and will be supplied in supplementary literature. during the programming process the res pin will be held low by the programmer disabling the normal opera - tion of the microcontroller and taking control of the pa0 and pa2 i/o pins for data and clock programming pur - poses. the user must there take care to ensure that no other outputs are connected to these two pins. programmer pin mcu pins res pc0 data pa0 clk pa2 programmer and mcu pins g g g " 8 + ( ) 2 " 8 + $ ) 2 + ( + " ! & ! ! note: * may be resistor or capacitor. the resistance of * must be greater than 1k or the capacitance of * must be less than 1nf. HT83F02 rev. 1.20 15 november 19, 2010 data memory the data memory is a volatile area of 8-bit wide ram in - ternal memory and is the location where temporary in - formation is stored. divided into two sections, the first of these is an area of ram where special function registers are located. these registers have fixed locations and are necessary for correct operation of the device. many of these registers can be read from and written to di - rectly under program control, however, some remain protected from user manipulation. the second area of ram data memory is reserved for general purpose use. all locations within this area are read and write accessi - ble under program control. structure the data memory has a bank, known as bank, which is implemented in 8-bit wide ram. the ram data memory is located in bank 0 which is also subdivided into two sec - tions, the special purpose data memory and the general purpose data memory. the length of these sections is dictated by the type of microcontroller chosen. the start address of the ram data memory for all de - vices is the address 00h , and the last data memory address is ffh . registers which are common to all microcontrollers, such as acc, pcl, etc., have the same data memory address. general purpose data memory all microcontroller programs require an area of read/write memory where temporary data can be stored and retrieved for use later. it is this area of ram memory that is known as general purpose data memory. this area of data memory is fully accessible by the user pro - gram for both read and write operations. by using the set [m].i and clr [m].i instructions individual bits can be set or reset under program control giving the user a large range of flexibility for bit manipulation in the data memory. special purpose data memory this area of data memory, is located in bank, where registers, necessary for the correct operation of the microcontroller, are stored. most of the registers are both readable and writable but some are protected and are readable only, the details of which are located under the relevant special function register section. note that for locations that are unused, any read instruction to these addresses will return the value 00h. special function registers to ensure successful operation of the microcontroller, certain internal registers are implemented in the data memory area. these registers ensure correct operation of internal functions such as timers, interrupts, etc., as ' $ ' 0 0 , , # , h $ ' - # 0 1 . 7 0 , ram data memory structure note: most of the ram data memory bits can be directly manipulated using the set [m].i and clr [m].i instructions with the exception of a few dedicated bits. the ram data memory can also be accessed through the memory pointer registers mp. 0 0 , 0 / , 0 # , 0 7 , 0 3 , 0 4 , 0 5 , 0 6 , 0 , 0 9 , 0 , 0 1 , 0 , 0 , 0 ( , 0 , / 0 , / / , / # , / 7 , / 3 , / 4 , / 5 , / 6 , / , / 9 , / , / 1 , / , / , / ( , / , # 0 , # / , # # , # 7 , # 3 , # 4 , # 5 , # 6 , # , # 9 , # , # 1 , # , # , # ( , # , 7 0 , , c & $ % > % i 0 0 i 0 0 ) 1 ) 1 ) , " & f 0 0 / / 1 1 f , 0 1 / 1 1 1 # 1 ) , " " ) " , + ) 0 / # , & special purpose data memory structure HT83F02 rev. 1.20 16 november 19, 2010 well as external functions such as i/o data control. the location of these registers within the data memory be - gins at the address 00h . any unused data memory lo - cations between these special function registers and the point where the general purpose memory begins is re - served and attempting to read data from these locations will return a value of 00h. indirect addressing register iar0 the indirect addressing registers, iar0, although hav - ing their locations in normal ram register space, do not actually physically exist as normal registers. the method of indirect addressing for ram data manipula - tion uses these indirect addressing registers and mem - ory pointers, in contrast to direct memory addressing, where the actual memory address is specified. actions on the iar0 registers will result in no actual read or write operation to these registers but rather to the memory lo - cation specified by their corresponding memory pointer, mp0. as the indirect addressing registers are not phys - ically implemented, reading the indirect addressing registers indirectly will return a result of 00h and writ - ing to the registers indirectly will result in no operation. memory pointer mp0 for all devices, two memory pointers, known as mp0 is provided. these memory pointers are physically imple - mented in the data memory and can be manipulated in the same way as normal registers providing a conve - nient way with which to address and track data. when any operation to the relevant indirect addressing regis - ters is carried out, the actual address that the microcontroller is directed to, is the address specified by the related memory pointer. the following example shows how to clear a section of four data memory locations already defined as locations adres1 to adres4. data .section data adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0 code org 00h start: mov a,04h ; setup size of block mov block,a mov a,offset adres1 ; accumulator loaded with first ram address mov mp0,a ; setup memory pointer with first ram address loop: clr iar0 ; clear the data at address defined by mp0 inc mp0 ; increment memory pointer sdz block ; check if last memory location has been cleared jmp loop continue: the important point to note here is that in the example shown above, no reference is made to specific data memory addresses. HT83F02 rev. 1.20 17 november 19, 2010 accumulator acc the accumulator is central to the operation of any microcontroller and is closely related with operations carried out by the alu. the accumulator is the place where all intermediate results from the alu are stored. without the accumulator it would be necessary to write the result of each calculation or logical operation such as addition, subtraction, shift, etc., to the data memory resulting in higher programming and timing overheads. data transfer operations usually involve the temporary storage function of the accumulator; for example, when transferring data between one user defined register and another, it is necessary to do this by passing the data through the accumulator as no direct transfer between two registers is permitted. program counter low register pcl to provide additional program control functions, the low byte of the program counter is made accessible to pro - grammers by locating it within the special purpose area of the data memory. by manipulating this register, direct jumps to other program locations are easily imple - mented. loading a value directly into this pcl register will cause a jump to the specified program memory lo - cation, however, as the register is only 8-bit wide, only jumps within the current program memory page are per- mitted. when such operations are used, note that a dummy cycle will be inserted. look-up table registers tblp, tblh these two special function registers are used to control operation of the look-up table, which is stored in the pro- gram memory. tblp is the table pointer and indicates the location where the table data is located. its value must be setup before any table read commands are ex - ecuted. its value can be changed, for example using the inc or dec instructions, allowing for easy table data pointing and reading. tblh is the location where the high order byte of the table data is stored after a table read data instruction has been executed. note that the lower order table data byte is transferred to a user de - fined location. watchdog timer register wdts the watchdog feature of the microcontroller provides an automatic reset function giving the microcontroller a means of protection against spurious jumps to incorrect program memory addresses. to implement this, a timer is provided within the microcontroller which will issue a reset command when its value overflows. to provide variable watchdog timer reset times, the watchdog timer clock source can be divided by various division ra - tios, the value of which is set using the wdts register. by writing directly to this register, the appropriate divi - sion ratio for the watchdog timer clock source can be setup. note that only the lower 3 bits are used to set divi - sion ratios between 1 and 128. status register status this 8-bit register contains the zero flag (z), carry flag (c), auxiliary carry flag (ac), overflow flag (ov), power down flag (pdf), and watchdog time-out flag (to). these arithmetic/logical operation and system manage - ment flags are used to record the status and operation of the microcontroller. with the exception of the to and pdf flags, bits in the status register can be altered by instructions like most other registers. any data written into the status register will not change the to or pdf flag. in addition, opera - tions related to the status register may give different re - sults due to the different instruction operations. the to flag can be affected only by a system power-up, a wdt time-out or by executing the clr wdt or halt in - struction. the pdf flag is affected only by executing the halt or clr wdt instruction or during a system power-up. the z, ov, ac and c flags generally reflect the status of the latest operations. c is set if an operation results in a carry during an ad- dition operation or if a borrow does not take place dur- ing a subtraction operation; otherwise c is cleared. c is also affected by a rotate through carry instruction. ac is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the high nib- ble into the low nibble in subtraction; otherwise ac is cleared. z is set if the result of an arithmetic or logical operation is zero; otherwise z is cleared. ov is set if an operation results in a carry into the high - est-order bit but not a carry out of the highest-order bit, or vice versa; otherwise ov is cleared. pdf is cleared by a system power-up or executing the clr wdt instruction. pdf is set by executing the halt instruction. to is cleared by a system power-up or executing the clr wdt or halt instruction. to is set by a wdt time-out. in addition, on entering an interrupt sequence or execut - ing a subroutine call, the status register will not be pushed onto the stack automatically. if the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it. HT83F02 rev. 1.20 18 november 19, 2010 interrupt control register intc, intch two 8-bit register, known as the intc and intch regis - ters, controls the operation of both external and internal timer interrupts. by setting various bits within these reg - isters using standard bit manipulation instructions, the enable/disable function of the external and timer inter - rupts can be independently controlled. a master inter - rupt bit within this register, the emi bit, acts like a global enable/disable and is used to set all of the interrupt en - able bits on or off. this bit is cleared when an interrupt routine is entered to disable further interrupt and is set by executing the reti instruction. note: in situations where other interrupts may require servicing within present interrupt service rou- tines, the emi bit can be manually set by the pro- gram after the present interrupt service routine has been entered. timer registers all devices contain two 8-bit timers whose associated registers are known as tmr0 and tmr1 which is the lo- cation where the associated timer's 8-bit value is lo - cated. their associated control registers, known as tmr0c and tmr1c, contain the setup information for these timers. note that all timer registers can be directly written to in order to preload their contents with fixed data to allow different time intervals to be setup. input/output ports and control registers within the area of special function registers, the i/o registers and their associated control registers play a prominent role. all i/o ports have a designated register correspondingly labeled as pa, pb and pc. these la - beled i/o registers are mapped to specific addresses within the data memory as shown in the data memory table, which are used to transfer the appropriate output or input data on that port. with each i/o port there is an associated control register labeled pac, pbc and pcc, also mapped to specific addresses with the data mem - ory. the control register specifies which pins of that port are set as inputs and which are set as outputs. to setup a pin as an input, the corresponding bit of the control register must be set high, for an output it must be set low. during program initialization, it is important to first setup the control registers to specify which pins are out- puts and which are inputs before reading data from or writing data to the i/o ports. one flexible feature of these registers is the ability to directly program single bits us- ing the set [m].i and clr [m].i instructions. the ability to change i/o pins from output to input and vice versa by manipulating specific bits of the i/o control reg - isters during normal program operation is a useful fea - ture of these devices. port c pull-high control register pcphc port c pull-high control register, pcphc, is used to set the port c pull high function. + j ! " ! # $ ? ! $ @ ? ! j ? ! ? * ? ! % & # # $ * % * ? ! " % ! $ ? ! f ' % > % i 0 i 6 0 status register 6 0 $ , ! / c 0 c % % ? $ f ' % > % i 0 i , 0 , / , # port c pull-high control register HT83F02 rev. 1.20 19 november 19, 2010 voice control and audio output registers dal, dah, vol the devices include a single 12-bit current type dac function for driving an external 8 speaker through an external npn transistor or power amplifier. the pro - grammer must writer the voice data to these dal/dah registers. the programmer can control the dac volume with 8-levels via the vol register. pulse width modulator registers pwmc, pwml, pwmh each device contains a single 12-bit pwm function for driving an external 8 speaker. the programmer must writer the voice data to pwml/pwmh register. the pro - grammer can control the pwm volume with 9-levels via the vol register. serial interface module(sim) registers simc0a/b, simc1a/b, simc2a/b, simara/b, simdra/b each sim contains spi and i 2 c function for communicat - ing with other microcontroller or spi flash memory. all devices contain an integrated i 2 c and spi bus which in - terfaces to the external shared pins sda, scl and scsb, sck, sdi, sdo with pb on the microcontroller. the i 2 c correct setup and data transfer operation of this 2-line bidirectional bus utilizes 4 special function regis- ters. the simara/b register sets the slave address of the device while the simc0a/b is the control register that enables or disables the device as well as select whether it is in i 2 c or spi mode. the simc1a/b register is the i 2 c status register while the simdra/b register is the input/output data register. the spi correct setup and data transfer operation of this 3-line bidirectional bus uti- lizes 3 special function registers. the simc0a/b is the control register that enables or disables the device as well as select whether it is in i 2 c or spi mode. the simc2a/b register is the spi status register while the simdra/b register is the input/output data register. input/output ports holtek microcontrollers offer considerable flexibility on their i/o ports. with the input or output designation of ev - ery pin fully under user program control, pull-high op - tions for all ports and wake-up options on certain pins, the user is provided with an i/o structure to meet the needs of a wide range of application possibilities. depending upon which device or package is chosen, the microcontroller range provides from 19 bidirectional input/output lines labeled with port names pa, pb, pc etc. these i/o ports are mapped to the data memory with specific addresses as shown in the special pur - pose data memory table. all of these i/o ports can be used for input and output operations. for input opera - tion, these ports are non-latching, which means the in - puts must be ready at the t2 rising edge of instruction mov a,[m] , where m denotes the port address. for output operation, all the data is latched and remains un - changed until the output latch is rewritten. pull-high resistors many product applications require pull-high resistors for their switch inputs usually requiring the use of an exter - nal resistor. to eliminate the need for these external re - sistors, all i/o pins, when configured as an input have the capability of being connected to an internal pull-high resistor. these pull-high resistors are selectable via configuration or software options and are implemented using a weak pmos transistor. note that if the pull-high option is selected, then all i/o pins on that port will be connected to pull-high resistors, individual pins can be selected for pull-high resistor options. port a wake-up each device has a halt instruction enabling the microcontroller to enter a power down mode and pre - serve power, a feature that is important for battery and other low-power applications. various methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the port a pins from high to low. after a halt instruction forces the microcontroller into entering a halt condition, the processor will re- main idle or in a low-power state until the logic condition of the selected wake-up pin on port a changes from high to low. this function is especially suitable for applica- tions that can be woken up via external switches. note that each pin on port a can be selected individually to have this wake-up feature. i/o port control registers each i/o port has its own control register pac, pbc and pcc, to control the input/output configuration. with this control register, each cmos output or input with or with - out pull-high resistor structures can be reconfigured dy - namically under software control. each pin of the i/o ports is directly mapped to a bit in its associated port control register. for the i/o pin to function as an input, the corresponding bit of the control register must be writ - ten as a 1 . this will then allow the logic state of the in - put pin to be directly read by instructions. when the corresponding bit of the control register is written as a 0 , the i/o pin will be setup as a cmos output. if the pin is currently setup as an output, instructions can still be used to read the output register. however, it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. HT83F02 rev. 1.20 20 november 19, 2010 pin-shared functions the flexibility of the microcontroller range is greatly en - hanced by the use of pins that have more than one func - tion. limited numbers of pins can force serious design constraints on designers but by supplying pins with multi-functions, many of these difficulties can be over - come. for some pins, the chosen function of the multi-function i/o pins is set by configuration options while for others the function is set by application pro - gram control. serial interface module the device pins, pb0~pb3, are pin-shared with pins sdab, sclb, scsb , sckb, sdib, sdob. the choice of which function is used is selected using the simc0b register. serial interface module the device pins, pb4~pb7, are pin-shared with pins sdaa, scla, scsa , scka, sdia, sdoa. the choice of which function is used is selected using the simc0a register. i/o pin structures the following diagrams illustrate the i/o pin internal structures. as the exact logical construction of the i/o pin may differ from these drawings, they are supplied as a guide only to assist with the functional under - standing of the i/o pins. note also that the specified pins refer to the largest device package, therefore not all pins specified will exist on all devices. + & k % ! l 2 l 2 1 $ , ! ' 1 $ " ! ' % ! " ! 1 ! * ' " $ $ ' l l & k 1 0 1 1 1 / 2 1 ) 1 1 # 1 1 7 1 1 3 1 4 2 ) 1 5 1 6 1 0 1 1 1 / 2 1 ) 1 1 # 1 1 7 1 1 3 1 4 2 ) 1 5 1 6 pb input/output port " $ ' ' " $ ' % ! 1 $ , ! ' 1 $ " ! ' % ! " ! 1 0 m 6 " $ $ ' l 2 l l 2 l + & k pa input/output port HT83F02 rev. 1.20 21 november 19, 2010 programming considerations within the user program, one of the first things to con - sider is port initialization. after a reset, all of the i/o data and port control registers will be set high. this means that all i/o pins will default to an input state, the level of which depends on the other connected circuitry and whether pull-high options have been selected. if the port control registers, pac, pbc, pcc etc., are then pro - grammed to setup some pins as outputs, these output pins will have an initial high output value unless the as - sociated port data registers, pa, pb, pc etc., are first programmed. selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct values into the appropriate port control register or by programming individual bits in the port control reg - ister using the set [m].i and clr [m].i instructions. note that when using these bit control instructions, a read-modify-write operation takes place. the microcontroller must first read in the data on the entire port, modify it to the required new bit values and then re - write this data back to the output ports. port a has the additional capability of providing wake-up functions. when the device is in the power down mode, various methods are available to wake the device up. one of these is a high to low transition of any of the port a pins. single or multiple pins on port a can be setup to have this function. timers the provision of timers form an important part of any microcontroller, giving the designer a means of carrying out time related functions. these devices contain two count up timers of 8-bit capacity. the provision of an in- ternal prescaler to the clock circuitry of the timer gives added range to the timer. there are two types of register related to each timer. the first is the register that contains the actual value of the timer and into which an initial value can be preloaded. reading from this register retrieves the con - tents of the timer. all devices can have the timer clock configured to come from the internal clock source. configuring the timer input clock source the clock source for the 8-bit timers is the system clock divided by four. the 8-bit timer clock source is also first di - vided by a, the division ratio of which is conditioned by the three lower bits of the associated timer control register. timer registers tmr0, tmr1 the timer registers are special function registers located in the special purpose data memory and is the place where the actual timer value is stored. all devices con - tain two 8-bit timers, whose registers are known as tmr0 and tmr1. the value in the timer registers in - creases by one each time an internal clock pulse is re - ceived. the timer will count from the initial value loaded by the preload register to the full count of ffh for the 8-bit timer at which point the timer overflows and an in - ternal interrupt signal is generated. the timer value will then be reset with the initial preload register value and continue counting. note that to achieve a maximum full range count of ffh for the 8-bit timer, the preload registers must first be cleared to all zeros. it should be noted that after power-on, the preload registers will be in an unknown condition. note that if the timer counters are in an off condition and data is written to their preload registers, this data will be immediately written into the actual coun- ter. however, if the counter is enabled and counting, any new data written into the preload data register during this period will remain in the preload register and will only be written into the actual counter the next time an overflow occurs. note also that when the timer registers are read, the timer clock will be blocked to avoid errors, however, as this may result in certain timing errors, pro - grammers must take this into account. / # 7 3 / # 7 3 " % ? read/write timing % 0 f / f % ! 1 $ % ? * $ ' / # m / 0 0 # m 0 0 1 $ ? b - / # m / # 4 5 . / / 0 / / 0 0 0 8-bit timer structure HT83F02 rev. 1.20 22 november 19, 2010 timer control registers tmr0c, tmr1c each timer has its respective timer control register, known as tmr0c and tmr1c. it is the timer control register together with their corresponding timer registers that control the full operation of the timers. before the timers can be used, it is essential that the appropriate timer control register is fully programmed with the right data to ensure its correct operation, a process that is normally carried out during program initialization. bits 7 and 6 of the timer control register, must be set to the required logic levels. bit 6 of the registers must always be written with a 1 , and bit 7 must always be written with a 0 . the timer-on bit, which is bit 4 of the timer control register and known as t0on/ t1on, depend - ing upon which timer is used, provides the basic on/off control of the respective timer. setting the bit high allows the timer to run, clearing the bit stops the timer. for the 8-bit timers, which have prescalers, bits 0~2 of the timer control register determines the division ratio of the input clock prescaler. configuring the timer the timer is used to measure fixed time intervals, pro - viding an internal interrupt signal each time the timer overflows. to do this the operating mode select bit pair in the timer control register must be set to the correct value as shown. control register operating mode select bits bit7 bit6 10 the internal clock, f sys , is used as the timer clock. how- ever, this clock source is further divided by a prescaler, the value of which is determined by the prescaler rate select bits, which are bits 0~2 in the timer control reg- ister. after the other bits in the timer control register have been setup, the enable bit, which is bit 4 of the timer control register, can be set high to enable the timer to run. each time an internal clock cycle occurs, the timer increments by one. when it is full and over - flows, an interrupt signal is generated and the timer will reload the value already loaded into the preload register and continue counting. the interrupt can be disabled by ensuring that the timer interrupt enable bit in the inter - rupt control register, intc, is reset to zero. prescaler all of the 8-bit timers possess a prescaler. bits 0~2 of their associated timer control register, define the pre-scaling stages of the internal clock source of the timer. the timer overflow signal can be used to gener - ate signals for the timer interrupt. programming considerations the internal system clock is used as the timer clock source and is therefore synchronized with the overall operation of the microcontroller. in this mode, when the appropriate timer register is full, the microcontroller will generate an internal interrupt signal directing the pro - gram flow to the respective internal interrupt vector. when the timer is read, the clock is blocked to avoid er - rors, however as this may result in a counting error, this should be taken into account by the programmer. care must be taken to ensure that the timers are properly ini - tialized before using them for the first time. the associ- ated timer enable bits in the interrupt control register must be properly set otherwise the internal interrupt associated with the timer will remain inactive. the edge select, timer mode and clock source control bits in timer control regis- ter must also be correctly set to ensure the timer is prop- erly configured for the required application. it is also important to ensure that an initial value is first loaded into the timer registers before the timer is switched on; this is because after power-on the initial values of the timer reg - isters are unknown. after the timer has been initialized the timer can be turned on and off by controlling the en - able bit in the timer control register. $ ' $ a / a # a f a f a / timer mode timing diagram HT83F02 rev. 1.20 23 november 19, 2010 6 f 0 / 0 f ' % > % i 0 i $ ! ( / c 0 c % ' ! % 0 / / / 0 0 / / 0 0 / 0 0 / 0 / % % % % & & ' f ' % > % i % n i # / 0 0 # / # 0 0 0 0 / / / / 0 / / / 0 0 / / 0 0 / / 0 0 / 0 0 / 0 / 0 / 0 / / c # / c 3 / c / c / 5 / c 7 # / c 5 3 / c / # / c # 4 5 timer control register (n=0 or 1) timer program example the following example program section is based on the device, which contain two 8-bit timers. programming the timer for other devices is conducted in a very similar way. the program shows how the timer registers are setup along with how the interrupts are enabled and managed. points to note in the example are how, for the 8-bit timer. note how the timer is turned on by setting bit 4 of the respective timer control register. the timer can be turned off in a similar way by clearing the same bit. this example program sets the timer to be in the timer mode which uses the internal fsys as their clock source, and produce a timer 0 interrupt per 1ms. #include HT83F02.inc jmp begin : org 04h ; time base vector reti org 08h ; timer 0 interrupt vector jmp tmr0int ; jump here when timer 0 overflows every 1ms org 0ch reti org 10h reti org 14h reti : ; internal timer 0 interrupt routine tmr0int: : ; timer 0 main program placed here : reti : begin: ; setup timer 0 registers mov a,06h ; setup timer 0 low byte mov tmr0,a ; flow byte must be setup before high byte mov a,094 ; setup timer 0 control register mov tmr0c,a ; setup timer mode and clock source is fsys/32 prescaler ; setup interrupt register mov a,05h ; enable global interrupt mov intc,a ; enable timer 0 interrupt HT83F02 rev. 1.20 24 november 19, 2010 time base the time base function will generate a regular interrupt signal synchronised to the system clock which can be used by the application as a time base signal. time base operation the time base operation is a very simple function for the generation of a regular time signal. this is imple - mented by generating a regular interrupt signal whose enable/disabled and request flags are in the intc regis - ter. the clock source for the time base is the internal f sys /4 clock source, which is then divided internally by a value of 1024. it is this divided signal that generates the internal interrupt. the time base interrupt is enabled by the etbi bit in the intc register and interrupt request flag is the tbf flag in the same register. a time base of 1ms will therefor be generated from a system clock of 4mhz and a time base of 0.5ms will be generated from a system clock source of 8mhz. time base example the following example program section is based on the device. the program shows how the time base regis - ters are setup along with how the interrupts are enabled and managed. the points to note in the example are how the time base is turned on by setting bit 4 of the intc register. the time base can be turned off in a sim - ilar way by clearing the same bit. this example program sets the time base which uses the internal system clock as their clock source, and produces a time base inter - rupt every 0.5ms from a system source clock of 8mhz. #include HT83F02.inc jmp begin : org 04h ; time base vector jmp time_base_int ; jump here when time base overflows per 0.5ms org 08h reti org 0ch reti org 10h reti org 14h reti : ; time base interrupt routine time_base_int: : ; time base main program placed here : reti : begin: ; setup interrupt register mov a,03h ; enable global and time base interrupt mov intc,a ; enable time base / 0 # 3 3 ? * $ ' HT83F02 rev. 1.20 25 november 19, 2010 serial interface the device contains both spi and i 2 c serial interface functions, which allows two methods of easy communi - cation with external peripheral hardware. as the spi and i 2 c function share the same external pins and internal registers their function must first be chosen by selecting the correct configuration option. spi interface the spi interface is often used to communicate with ex - ternal peripheral devices such as sensors, flash or eeprom memory devices etc. originally developed by motorola, the four line spi interface is a synchronous serial data interface that has a relatively simple commu - nication protocol simplifying the programming require - ments when communicating with external hardware devices. spi interface operation the spi interface is a full duplex synchronous serial data link. communication between devices con - nected to the spi interface is carried out in a slave/master mode with all data transfer initiations be - ing implemented by the master. multiple slave devices can be connected to the spi serial bus with each de - vice controlled using its slave select line. the spi is a four line interface with pin names sdi, sdo, sck and scs . pins sdi and sdo are the serial data input and serial data output lines, sck is the serial clock line and scs is the slave select line. as the spi interface pins are pin-shared with segment pins and with the i 2 c function pins, the spi interface must first be enabled by selecting the correct configuration option. after the spi configuration option has been selected it can then also be selected using the simen bit in the simc0 register. the spi function in this device offers the following fea - tures: full duplex synchronous data transfer both master and slave modes lsb first or msb first data transmission modes transmission complete flag several other configuration options also exist to setup various spi interface options as follows: spi pin enabled wcol bit enabled or disabled csen bit enabled or disabled the status of the spi interface pins is determined by a number of factors, whether the device is in master or slave mode and upon the condition of cer - tain control bits such as csen and simen. 6 5 4 3 7 # / 0 - % ! . & k 1 $ ? ? & k ) 1 $ & k 1 $ % 2 # / 0 ( f 1 $ ! ( f " " ) ! % > ( f ( f f " 1 " ( ( f ( f ( f % > % > block diagram HT83F02 rev. 1.20 26 november 19, 2010 master/salve ( simen =0) master ( simen =1) slave ( simen =1) csen=1 csen=0 csen=0 scs line=0 (csen=1) scs line=1 (csen=1) scs zl z zi , zi , z s d ozooooz sdi z i, z i, z i, z i, z z sck z l(cpol=1) h(cpol=0) l(cpol=1) h(cpol=0) i, z i, z z z floating, h output high, l output low, i input, o output level, i,z input floating (no pull-high) spi interface pin status spi registers the simdr a/b register is used to store the data be - ing transmitted and received. there are two control registers associated with the spi interface, simc0 a/b and simc2 a/b and one data register known as simdra/b. the simc1 a/b register is not used by the spi function. register simc0 a/b is used to control the enable/disable function, the power down control and to set the data transmission clock frequency. reg - ister simc2 a/b is used for other control functions such as lsb/msb selection, write collision flag etc. the following gives further explanation of each bit: simen a/b the simen a/b bit is the overall on/off control for the spi interface. when the simen a/b bit is cleared to zero to disable the spi interface, the sdi, sdo a/b, sck a/b and scs a/b lines will be in a floating condition and the spi operating current will be reduced to <0.1 a at 5v. when the bit is high the spi interface is enabled. note that when the simen a/b bit changes from low to high the contents of the spi control registers will be in an unknown condition and should therefore be initialised by the applica - tion program. sim0 a/b~sim2 a/b these three bits control the master/slave selection and also setup the spi interface clock speed when in the master mode. the spi clock is a function of the system clock whether it be rc type or crystal type. if the slave mode is selected then the clock will be supplied by the external master device. the following gives further explanation of each bit: trf a/b the trf a/b bit is the transmit/receive complete flag and is cleared by the application program and can be used to generate an interrupt. when the bit is high the data has been transmitted or received. if the bit is low the data is being transmitted or has not yet been received. wcol a/b the wcol a/b bit is used to detect if a data colli - sion has occurred. if this bit is high it means that data has been attempted to be written to the smdr a/b register during a data transfer operation. this writing operation will be ignored if data is being transferred. the bit can be cleared by the applica - tion program. note that using the csen a/b bit can be disabled or enabled via configuration option. csen a/b the csen a/b bit is used as an on/off control for the scs a/b pin. if this bit is low then the scs a/b pin will be disabled and placed into a floating condition. if the bit is high the scs a/b pin will be enabled and used as a select pin. mls a/b the mls a/b is used to select how the data is trans- ferred, either msb or lsb first. setting the bit high will select msb first and low for lsb first. note that the simc2 a/b register is the same as the simar a/b register used by the i 2 c interface. spi communication after the spi interface is enabled by setting the simen a/b bit high, then in the master mode, when data is written to the simdr a/b register, transmis - sion/reception will begin simultaneously. when the data transfer is complete, the trf a/b flag will be set automatically. in the slave mode, when the clock sig - nal from the master has been received, any data in the simdr register will be transmitted and any data on the sdi a/b pin will be shifted into the simdr a/b reg - ister. the master should output an scs a/b signal be - fore a clock signal is provided and slave data transfers should be enabled/disabled before/after an scs a/b signal is received. HT83F02 rev. 1.20 27 november 19, 2010 2 - 2 ) 1 < / . 2 - 2 ) 1 < 0 . ' $ 6 0 5 / 4 # 3 7 7 3 # 4 / 5 0 6 " - % ! $ ? 2 % ! . spi slave mode timing ckeg=0 2 - 2 ) 1 < / > 2 ( h < 0 . ( f > ( f < / ( f < / > ( f < 0 - ( @ $ , ! . 2 - 2 ) 1 < 0 > 2 ( h < 0 . 2 - 2 ) 1 < / > 2 ( h < / . 2 - 2 ) 1 < 0 > 2 ( h < / . - 2 ( h < 0 . - 2 ( h < / . ' $ 6 0 5 / 4 # 3 7 7 3 # 4 / 5 0 6 6 0 5 / 4 # 3 7 7 3 # 4 / 5 0 6 " spi master mode timing 2 - 2 ) 1 < / . 2 - 2 ) 1 < 0 . ' $ 6 0 5 / 4 # 3 7 7 3 # 4 / 5 0 6 " - ! * ! $ o ? ! ? < / . f c % > ? ( f < / % ( f < 0 > * % % ! = spi slave mode timing ckeg=1 HT83F02 rev. 1.20 28 november 19, 2010 ( & ) f ' % > % i 0 i ? ? / c 0 c % f ' % % # 1 / 1 0 1 0 ( f 1 > ? b 3 > ? b / 5 > ? b 5 3 > ? b % % % 0 0 0 0 / / / / 0 0 / / 0 0 / / 6 / 1 0 1 # 1 0 / 0 / 0 / 0 / spi control register simc0a/b ( & ) 6 ' ? ! / c % ? ' 0 c % ? ' " ? ! / c % 0 c 1 ' / c 0 c % > 1 ? ! ? % / c 1 ? 0 c ) 1 ? % ! / c ? ! % ! 0 c ! % ! ' / c * 0 c ! f ' % > % i 0 i 0 " ) 1 1 ( f 1 ) 1 2 ( h 1 2 ) 1 spi control register simc2a/b HT83F02 rev. 1.20 29 november 19, 2010 ( f < / " " ) < / p " ) b ' % p - < / p . f b % ? ? % p f b ( f ? ? ! $ ( f % ) d # c 0 e < 0 0 0 > 0 0 / > 0 / 0 > 0 / / d # c 0 e < / 0 / spi transfer control flowchart HT83F02 rev. 1.20 30 november 19, 2010 i 2 c interface the i 2 c bus is a bidirectional 2-line communication inter - face originally developed by philips. the possibility of transmitting and receiving data on only 2 lines offers many new application possibilities for microcontroller based applications. i 2 c interface operation as the i 2 c interface pins are pin-shared with segment pins and with the spi function pins, the i 2 c interface must first be enabled by selecting the correct configu - ration option. there are two lines associated with the i 2 c bus, the first is known as sda and is the serial data line, the second is known as scl line and is the serial clock line. as many devices may be connected together on the same bus, their outputs are both open drain types. for this reason it is necessary that external pull-high resistors are connected to these outputs. note that no chip select line exists, as each device on the i 2 c bus is identified by a unique address which will be transmit - ted and received on the i 2 c bus. when two devices communicate with each other on the bidirectional i 2 c bus, one is known as the master device and one as the slave device. both master and slave can transmit and receive data, however, it is the master device that has overall control of the bus. for this device, which only operates in slave mode, there are two methods of transferring data on the i 2 c bus, the slave transmit mode and the slave receive mode. i 2 c registers there are three control registers associated with the i 2 c bus, simc0a/b, simc1a/b and simara/b and one data register, simdra/b. the simdra/b register is used to store the data being transmitted and received on the i 2 c bus. before the microcontroller writes data to the i 2 c bus, the actual data to be transmitted must be placed in the simdra/b register. after the data is received from the i 2 c bus, the microcontroller can read it from the simdra/b register. any transmission of data to the i 2 c bus or reception of data from the i 2 c bus must be made via the simdra/b register. the simara/b register is the location where the slave address of the microcontroller is stored. bits 1~7 of the simara/b register define the microcontroller slave address. bit 0 is not defined. when a master de - vice, which is connected to the i 2 c bus, sends out an address, which matches the slave address in the simara/b register, the microcontroller slave device will be selected. note that the simara/b register is the same register as simc2a/b which is used by the spi interface. the simc0a/b register is used for the i 2 c overall on/off control. i 2 c configuration option there are several configuration options associated with the i 2 c interface. one of these is to enable the rnica/b bit function which selects the rnica/b bit in simc1a/b register. another configuration option de - termines the debounce time of the i 2 c interface. this add a debounce delay time to the external clock to re - duce the possibility of glitches on the clock line caus- ing erroneous operation. the debounce time if selected can be chosen to be either 1 or 2 system clocks. ( & ) 6 f ' % > % i 0 i # % % % 0 4 1 3 1 5 1 0 1 7 1 # 1 / 1 slave address register simara/b ( & ) f ' % > % i 0 i # ? ? / c 0 c % f ' % # % # 1 / 1 0 1 0 ( f 1 f $ % f $ % f $ % f $ % f $ % f $ % # % f $ % 0 0 0 0 / / / / 0 0 / / 0 0 / / 0 / 0 / 0 / 0 / 6 / 1 0 1 # 1 i 2 c control register simc0a/b HT83F02 rev. 1.20 31 november 19, 2010 the following gives further explanation of each bit: simena/b the simena/b bit determines if the i 2 c bus is en- abled or disabled. if data is to be transferred or re- ceived on the i 2 c bus then this bit must be set high. the following gives further explanation of each bit: hcfa/b the hcfa/b flag is the data transfer flag. this flag will be zero when data is being transferred. upon completion of an 8-bit data transfer the flag will go high and an interrupt will be generated. hassa/b the hassa/b flag is the address match flag. this flag is used to determine if the slave device address is the same as the master transmit address. if the addresses match then this bit will be high, if there is no match then the flag will be low. hbba/b the hbba/b flag is the i 2 c busy flag. this flag will be high when the i 2 c bus is busy which will occur when a start signal is detected. the flag will be reset to zero when the bus is free which will occur when a stop signal is detected. htxa/b the htxa/b flag is the transmit/receive mode bit. this flag should be set high to set the transmit mode and low for the receive mode. txaka/b the txaka/b flag is the transmit acknowledge flag. after the receipt of 8-bits of data, this bit will be transmitted to the bus on the 9th clock. to continue receiving more data, this bit has to be reset to zero before further data is received. srwa/b the srwa/b bit is the slave read/write bit. this bit determines whether the master device wishes to transmit or receive data from the i 2 c bus. when the transmitted address and slave address match, that is when the haasa/b bit is set high, the device will check the srwa/b bit to determine whether it should be in transmit mode or receive mode. if the srwa/b bit is high, the master is requesting to read data from the bus, so the device should be in trans- mit mode. when the srwa/b bit is zero, the master will write data to the bus, therefore the device should be in receive mode to read this data. rnica/b the rnica/b bit is used as i 2 c running clock from internal or external clock. if this bit is low then i 2 c running using internal clock and it will not wake-up when i 2 c interrupts in the power down mode. if the bit is high i 2 c running using external clock and it will wake-up when i 2 c interrupts in the power down mode. rxaka/b the rxaka/b flag is the receive acknowledge flag. when the rxaka/b bit has been reset to zero it means that a correct acknowledge signal has been received at the 9th clock, after 8 bits of data have been transmitted. when in the transmit mode, the transmitter checks the rxaka/b bit to determine if the receiver wishes to receive the next byte. the transmitter will therefore continue sending out data until the rxaka/b bit is set to 1 . when this oc - curs, the transmitter will release the sdaa/b line to allow the master to send a stop signal to release the bus. ( & ' ) 6 * % ! ? ! / c * % ! % 0 c * % ! % # $ ! / c # $ ! $ ! 0 c # $ ! $ ! % % * : $ ? ! / c : $ % % 0 c : $ % * * % ! ? ! / c % n * % ! 0 c * % ! % / c % 0 c % # $ $ ? ! / c $ 0 c $ ! % % % ? ! / c % 0 c % ? ? ! / c ? ' 0 c ? ' 0 , k 1 k 2 1 " 1 k 2 1 , 1 1 1 , 1 , 1 f 1 i 2 c control register simc1a/b HT83F02 rev. 1.20 32 november 19, 2010 ! ? % % % % " ? * % ! ? % % ? * % ! ? ! ? i 2 c bus communication communication on the i 2 c bus requires four separate steps, a start signal, a slave device address transmis - sion, a data transmission and finally a stop signal. when a start signal is placed on the i 2 c bus, all de - vices on the bus will receive this signal and be notified of the imminent arrival of data on the bus. the first seven bits of the data will be the slave address with the first bit being the msb. if the address of the microcontroller matches that of the transmitted address, the haas bit in the simc1 register will be set and an i 2 c interrupt will be generated. after entering the interrupt service routine, the microcontroller slave device must first check the condition of the haas bit to determine whether the inter- rupt source originates from an address match or from the completion of an 8-bit data transfer. during a data transfer, note that after the 7-bit slave address has been transmitted, the following bit, which is the 8th bit, is the read/write bit whose value will be placed in the srw bit. this bit will be checked by the microcontroller to deter - mine whether to go into transmit or receive mode. be - fore any transfer of data to or from the i 2 c bus, the microcontroller must initialise the bus, the following are steps to achieve this: step 1 write the slave address of the microcontroller to the i 2 c bus address register simar. step 2 set the simen bit in the simc0 register to 1 to enable the i 2 c bus. step 3 set the ehi bit of the interrupt control register to enable the i 2 c bus interrupt. start signal the start signal can only be generated by the mas - ter device connected to the i 2 c bus and not by the microcontroller, which is only a slave device. this start signal will be detected by all devices con - nected to the i 2 c bus. when detected, this indicates that the i 2 c bus is busy and therefore the hbb bit will be set. a start condition occurs when a high to low transition on the sda line takes place when the scl line remains high. slave address the transmission of a start signal by the master will be detected by all devices on the i 2 c bus. to deter- mine which slave device the master wishes to com- municate with, the address of the slave device will be sent out immediately following the start signal. all slave devices, after receiving this 7-bit address data, will compare it with their own 7-bit slave address. if the address sent out by the master matches the internal address of the microcontroller slave device, then an internal i 2 c bus interrupt signal will be generated. the next bit following the address, which is the 8th bit, de - fines the read/write status and will be saved to the srw bit of the simc1 register. the device will then transmit an acknowledge bit, which is a low level, as the 9th bit. the microcontroller slave device will also set the status flag haas when the addresses match. as an i 2 c bus interrupt can come from two sources, when the program enters the interrupt subroutine, the haas bit should be examined to see whether the in - terrupt source has come from a matching slave ad - dress or from the completion of a data byte transfer. when a slave address is matched, the device must be placed in either the transmit mode and then write data to the simdr register, or in the receive mode where it must implement a dummy read from the simdr regis - ter to release the scl line. HT83F02 rev. 1.20 33 november 19, 2010 srw bit the srw bit in the simc1 register defines whether the microcontroller slave device wishes to read data from the i 2 c bus or write data to the i 2 c bus. the microcontroller should examine this bit to determine if it is to be a transmitter or a receiver. if the srw bit is set to 1 then this indicates that the master wishes to read data from the i 2 c bus, therefore the microcontroller slave device must be setup to send data to the i 2 c bus as a transmitter. if the srw bit is 0 then this indicates that the master wishes to send data to the i 2 c bus, therefore the microcontroller slave device must be setup to read data from the i 2 c bus as a receiver. acknowledge bit after the master has transmitted a calling address, any slave device on the i 2 c bus, whose own internal address matches the calling address, must generate an acknowledge signal. this acknowledge signal will inform the master that a slave device has accepted its calling address. if no acknowledge signal is received by the master then a stop signal must be transmitted by the master to end the communication. when the haas bit is high, the addresses have matched and the microcontroller slave device must check the srw bit to determine if it is to be a transmitter or a receiver. if the srw bit is high, the microcontroller slave device should be setup to be a transmitter so the htx bit in the simc1 register should be set to 1 if the srw bit is low then the microcontroller slave device should be setup as a receiver and the htx bit in the simc1 reg - ister should be set to 0. data byte the transmitted data is 8-bits wide and is transmitted after the slave device has acknowledged receipt of its slave address. the order of serial bit transmission is the msb first and the lsb last. after receipt of 8-bits of data, the receiver must transmit an acknowledge sig - nal, level 0 , before it can receive the next data byte. if the transmitter does not receive an acknowledge bit signal from the receiver, then it will release the sda line and the master will send out a stop signal to re- lease control of the i 2 c bus. the corresponding data will be stored in the simdr register. if setup as a transmitter, the microcontroller slave device must first write the data to be transmitted into the simdr regis- ter. if setup as a receiver, the microcontroller slave de- vice must read the transmitted data from the simdr register. receive acknowledge bit when the receiver wishes to continue to receive the next data byte, it must generate an acknowledge bit, known as txak, on the 9th clock. the microcontroller slave device, which is setup as a transmitter will check the rxak bit in the simc1 register to determine if it is to send another data byte, if not then it will release the sda line and await the receipt of a stop signal from the master. / 0 / 0 0 / 00 / 0 0 / 0 / 0 / / < - / . < % % - 6 . < " - / . < % % * % ! - / . < - . < 2 - k 2 ? > k 2 ? / . < ' - / . ) " 2 2 ' ) % % i 2 c communication timing diagram ) * ! ' data timing diagram HT83F02 rev. 1.20 34 november 19, 2010 , < / p , k < / p " < / p b f b f k 2 < / p b f f % ? ( b $ % ? ( ( " ( , k " $ % ) , k ) k 2 ( ( ) , k ) k 2 i 2 c bus isr flow chart " % % ( d # c 0 e < / / 0 ( ( f # 1 $ $ ' < p ( ( ( " ? $ ' h ! ) ( % % * ! # 1 $ h ! i 2 c bus initialisation flow chart HT83F02 rev. 1.20 35 november 19, 2010 interrupts interrupts are an important part of any microcontroller system. when an internal function such as a time base or timer requires microcontroller attention, their corre - sponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to di - rect attention to their respective needs. each device contains a time base interrupt and two internal timer in - terrupt functions. the time base interrupt is controlled by bit 1 of intc register, while the internal interrupt is controlled by the timer counter overflow. interrupt register overall interrupt control, which means interrupt enabling and flag setting, is controlled using two registers, known as intc and intch, which are located in the data memory. by controlling the appropriate enable bits in these registers each individual interrupt can be enabled or disabled. also when an interrupt occurs, the corre - sponding request flag will be set by the microcontroller. the global enable flag if cleared to zero will disable all interrupts. interrupt operation a timer or time base overflow or by setting their corre - sponding request flag, if their appropriate interrupt en- able bit is set. when this happens, the program counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. the program counter will then be loaded with a new ad- dress which will be the value of the corresponding inter- rupt vector. the microcontroller will then fetch its next instruction from this interrupt vector. the instruction at this vector will usually be a jmp statement which will take program execution to another section of program which is known as the interrupt service routine. here is located the code to control the appropriate interrupt. the interrupt service routine must be terminated with a reti statement, which retrieves the original program counter address from the stack and allows the microcontroller to continue with normal execution at the point where the in - terrupt occurred. the various interrupt enable bits, together with their as - sociated request flags, are shown in the accompanying diagram with their order of priority. once an interrupt subroutine is serviced, all the other in - terrupts will be blocked, as the emi bit will be cleared au - tomatically. this will prevent any further interrupt nesting from occurring. however, if other interrupt requests oc - cur during this interval, although the interrupt will not be immediately serviced, the request flag will still be re - corded. if an interrupt requires immediate servicing while the program is already in another interrupt service routine, the emi bit should be set after entering the rou - tine, to allow interrupt nesting. if the stack is full, the in - terrupt request will not be acknowledged, even if the related interrupt is enabled, until the stack pointer is decremented. if immediate service is desired, the stack must be prevented from becoming full. ( * 6 0 ( 0 ( 1 ( 1 0 ( / / $ ' h ( / c ! 0 c ! % 1 $ ' ( / c 0 c % 0 $ ' ( / c 0 c % / $ ' ( / c 0 c % 1 $ ' : $ ! / c 0 c 0 $ ' : $ ! / c 0 c / $ ' : $ ! / c 0 c f ' % > % i 0 i interrupt control register HT83F02 rev. 1.20 36 november 19, 2010 interrupt priority interrupts, occurring in the interval between the rising edges of two consecutive t2 pulses, will be serviced on the latter of the two t2 pulses, if the corresponding inter - rupts are enabled. in case of simultaneous requests, the accompanying table shows the priority that is applied. interrupt source interrupt vector HT83F02 priority time base interrupt 04h 1 timer 0 overflow 08h 2 timer 1 overflow 0ch 3 sim a interrupt 10h 4 sim b interrupt 14h 5 suitable masking of the individual interrupts using the intc and intch registers can prevent simultaneous occurrences. time base interrupt each device contains a time base whose correspond - ing interrupt enable bits are known as etbi and is lo - cated in the intc register. for a time base generated interrupt to occur, the corresponding time base inter - rupt enable bit must be first set. time base also has a corresponding time base interrupt request flag, which is known as tbf, also located in the intc register. when the master interrupt and corresponding timer in - terrupt enable bits are enabled, the stack is not full, and when the corresponding timer overflows a subroutine call to the corresponding time base interrupt vector will occur. the corresponding program memory vector loca - tions for the time base is 04h. after entering the inter - rupt execution routine, the corresponding interrupt request flag, tbf will be reset and the emi bit will be cleared to disable other interrupts. ( * 6 0 1 ( 1 ? $ ' / c 0 c % ? 1 $ ' / c 0 c % f ' % > % i 0 i ? $ ' : $ ? ! / c 0 c ? $ ' 1 : $ ? ! / c 0 c f ' % > % i 0 i ( intch register $ % $ % ? * ( ( ( $ ' ! , ! $ % ( % $ ( 0 ( / ( 0 $ ' : $ ! 0 / $ ' : $ ! / $ ' : $ ! 1 : $ ! ( ) * ( 1 1 $ ' : $ ! 1 interrupt structure HT83F02 rev. 1.20 37 november 19, 2010 timer interrupt for a timer generated interrupt to occur, the correspond - ing timer interrupt enable bit must be first set. each de - vice contains two 8-bit timers whose corresponding interrupt enable bits are known as et0 and et1and are located in the intc register. each timer also has a cor - responding timer interrupt request flag, which are known as t0f and t1f, also located in the intc regis - ter. when the master interrupt and corresponding timer interrupt enable bits are enabled, the stack is not full, and when the corresponding timer overflows a subrou - tine call to the corresponding timer interrupt vector will occur. the corresponding program memory vector loca - tions for timer 0 and timer1 are 08h and 0ch. after en - tering the interrupt execution routine, the corresponding interrupt request flags, t0f or t1f will be reset and the emi bit will be cleared to disable other interrupts. serial interface module - sim - interrupt sima/b interrupts include both the spi and i 2 c inter - rupts. the sima/b mode is determined by the sim2a/b, sim1a/b and sim0a/b bits in the simc0a/b register. for a spi interrupt to occur, the global interrupt enable bit, emi, and the corresponding sima/b interrupt enable bit, esii, must be first set. the simena/b bit in the simc0a/b register must also be set. an actual spi in- terrupt will take place when the flag, sifa/b, is set, a sit- uation that will occur when 8-bits of data are transferred or received from either of the spi interfaces. when the interrupt is enabled, the stack is not full and an sima/b interrupt occurs, a subroutine call to the sima/b inter- rupt vector at location 10h, will take place. when the in- terrupt is serviced, the spia/b interrupt request flag, sifa/b, will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. for an i 2 c interrupt to occur, the corresponding interrupt enable bit esiia/b must be first set. an actual i 2 c inter - rupt will be initialized when the sima/b interrupt request flag, sifa/b, is set, a situation that will occur when a matching i 2 c slave address is received or from the com - pletion of an i 2 c data byte transfer. when the interrupt is enabled, the stack is not full and a sima/b interrupt oc - curs, a subroutine call to the sima/b interrupt vector at location 14h, will take place when an i 2 c interrupt oc - curs, the interrupt request flag sifa/b will be reset and the emi bit will be cleared to disable other interrupts. programming considerations by disabling the interrupt enable bits, a requested inter - rupt can be prevented from being serviced, however, once an interrupt request flag is set, it will remain in this condition in the intc or intch register until the corre - sponding interrupt is serviced or until the request flag is cleared by a software instruction. it is recommended that programs do not use the call subroutine instruction within the interrupt subroutine. interrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. if only one stack is left and the interrupt is not well con - trolled, the original control sequence will be damaged once a call subroutine is executed in the interrupt subroutine. all of these interrupts have the capability of waking up the processor when in the power down mode. only the program counter is pushed onto the stack. if the con- tents of the register or status register are altered by the interrupt service program, which may corrupt the de- sired control sequence, then the contents should be saved in advance. HT83F02 rev. 1.20 38 november 19, 2010 reset and initialisation a reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. the most important reset condition is after power is first applied to the microcontroller. in this case, internal circuitry will ensure that the microcontroller, af - ter a short delay, will be in a well defined state and ready to execute the first program instruction. after this power-on reset, certain important internal registers will be set to defined states before the program com - mences. one of these registers is the program counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest program memory address. in addition to the power-on reset, situations may arise where it is necessary to forcefully apply a reset condition when the microcontroller is running. one example of this is where after power has been applied and the microcontroller is already running, the res line is force - fully pulled low. in such a case, known as a normal oper - ation reset, some of the microcontroller registers remain unchanged allowing the microcontroller to proceed with normal operation after the reset line is allowed to return high. another type of reset is when the watchdog timer overflows and resets the microcontroller. all types of re- set operations result in different register conditions be- ing setup. reset functions there are five ways in which a microcontroller reset can occur, through events occurring both internally and ex- ternally: power-on reset the most fundamental and unavoidable reset is the one that occurs after power is first applied to the microcontroller. as well as ensuring that the program memory begins execution from the first memory ad - dress, a power-on reset also ensures that certain other registers are preset to known conditions. all the i/o port and port control registers will power up in a high condition ensuring that all pins will be first set to inputs. although the microcontroller has an internal rc reset function, if the vdd power supply rise time is not fast enough or does not stabilise quickly at power-on, the internal reset function may be incapable of providing proper reset operation. for this reason it is recom - mended that an external rc network is connected to the res pin, whose additional time delay will ensure that the res pin remains low for an extended period to allow the power supply to stabilise. during this time delay, normal operation of the microcontroller will be inhibited. after the res line reaches a certain voltage value, the reset delay time t rstd is invoked to provide an extra delay time after which the microcontroller will begin normal operation. the abbreviation sst in the figures stands for system start-up timer. for most applications a resistor connected between vdd and the res pin and a capacitor connected be - tween vss and the res pin will provide a suitable ex - ternal reset circuit. any wiring connected to the res pin should be kept as short as possible to minimise any stray noise interference. for applications that operate within an environment where more noise is present the enhanced reset cir - cuit shown is recommended. more information regarding external reset circuits is located in application note ha0075e on the holtek website. res pin reset this type of reset occurs when the microcontroller is already running and the res pin is forcefully pulled low by external hardware such as an external switch. in this case as in the case of other reset, the program counter will reset to zero and program execution initi - ated from this point. ( + $ 0 = 9 + power-on reset timing chart ( 0 = / / 0 0 + + 0 = 0 / / 0 enhanced reset circuit ( $ 0 = 9 + 0 = 3 + res reset timing chart ( + + 0 = / / 0 0 basic reset circuit HT83F02 rev. 1.20 39 november 19, 2010 watchdog time-out reset during normal operation the watchdog time-out reset during normal opera - tion is the same as a hardware res pin reset except that the watchdog time-out flag to will be set to 1. watchdog time-out reset during power down the watchdog time-out reset during power down is a little different from other kinds of reset. most of the conditions remain unchanged except that the pro - gram counter and the stack pointer will be cleared to 0 and the to flag will be set to 1 . refer to the a.c. characteristics for t sst details. reset initial conditions the different types of reset described affect the reset flags in different ways. these flags, known as pdf and to are located in the status register and are controlled by various microcontroller operations, such as the power down function or watchdog timer. the reset flags are shown in the table: to pdf reset conditions 0 0 res reset during power-on u u res or lvr reset during normal operation 1 u wdt time-out reset during normal operation 1 1 wdt time-out reset during power down note: u stands for unchanged the following table indicates the way in which the vari - ous components of the microcontroller are affected after a power-on reset occurs. item condition after reset program counter reset to zero interrupts all interrupts will be disabled wdt clear after reset, wdt begins counting timer all timer will be turned off prescaler the timer prescaler will be cleared input/output ports i/o ports will be setup as inputs stack pointer stack pointer will point to the top of the stack " $ $ wdt time-out reset during normal operation timing chart " $ $ wdt time-out reset during power down timing chart HT83F02 rev. 1.20 40 november 19, 2010 the different kinds of resets all affect the internal registers of the microcontroller in different ways. to ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. the following table describes how each type of reset affects each of the microcontroller internal registers. note that where more than one package type exists the table will reflect the situation for the larger package type. register reset (power-on) wdt time-out (normal operation) res reset (normal operation) res reset (halt) wdt time-out from halt mp0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu acc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu pcl 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 tblp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tblh xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu wdts 0000 0111 0000 0111 0000 0111 0000 0111 uuuu uuuu status 00 xxxx 1u uuuu uu uuuu 01 uuuu 11 uuuu intc 000 0000 000 0000 000 0000 000 0000 uuu uuuu tmr0 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu tmr0c 0100 0000 0100 0000 0100 0000 0100 0000 uuuu uuuu tmr1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu tmr1c 0100 0000 0100 0000 0100 0000 0100 0000 uuuu uuuu pa 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pac 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pb 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pbc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pc 111 111 111 111 uuu pcc 111 111 111 111 uuu intch 00 00 00 00 00 00 00 00 uu uu dal xxxx uuuu uuuu uuuu uuuu dah xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu pwmc 0 0000 0 0000 0 0000 0 0000 u uuuu pwml xxxx uuuu uuuu uuuu uuuu pwmh xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu vol xxxx xxx uuuu uuu uuuu uuu uuuu uuu uuuu uuu simc0a 111x xx0 111x xx0 111x xx0 111x xx0 uuux xxu simc1a 100x x0x1 100x x0x1 100x x0x1 100x x0x1 uuux xuxu simdra xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx simara/ simc2a 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu simc0b 111x xx0 111x xx0 111x xx0 111x xx0 uuux xxu simc1b 100x x0x1 100x x0x1 100x x0x1 100x x0x1 uuux xuxu simdrb xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx simarb/ simc2b 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu pcphc 000 000 000 000 uuu note: u stands for unchanged x stands for unknown stands for undefined HT83F02 rev. 1.20 41 november 19, 2010 oscillator various oscillator options offer the user a wide range of functions according to their various application require - ments. three types of system clocks can be selected while various clock source options for the watchdog timer are provided for maximum flexibility. all oscillator options are selected through the configuration options. the three methods of generating the system clock are: external crystal/resonator oscillator external rc oscillator internal rc oscillator one of these three methods must be selected using the configuration options. more information regarding the oscillator is located in application note ha0075e on the holtek website. external crystal/resonator oscillator the simple connection of a crystal across osc1 and osc2 will create the necessary phase shift and feed - back for oscillation, and will normally not require exter - nal capacitors. however, for some crystals and most resonator types, to ensure oscillation and accurate fre - quency generation, it may be necessary to add two small value external capacitors, c1 and c2. the exact values of c1 and c2 should be selected in consultation with the crystal or resonator manufacturer s specifica- tion. the external parallel feedback resistor, rp, is nor- mally not required but in some cases may be needed to assist with oscillation start up. internal ca, cb, rf typical values @ 5v, 25 c ca cb rf 11~13pf 13~15pf 800k oscillator internal component values external rc oscillator using the external system rc oscillator requires that a resistor, with a value between 150k and 300k ,iscon - nected between osc1 and vss. the generated system clock divided by 4 will be provided on osc2 as an out - put which can be used for external synchronization pur - poses. note that as the osc2 output is an nmos open-drain type, a pull high resistor should be con - nected if it to be used to monitor the internal frequency. although this is a cost effective oscillator configuration, the oscillation frequency can vary with vdd, tempera - ture and process variations and is therefore not suitable for applications where timing is critical or where accu - rate oscillator frequencies are required. for the value of the external resistor r osc refer to the holtek website for typical rc oscillator vs. temperature and vdd charac - teristics graphics. note that it is the only microcontroller internal circuitry together with the external resistor, that determine the frequency of the oscillator. the external capacitor shown on the diagram does not influence the frequency of oscillation. internal rc oscillator the internal rc oscillator is a fully integrated system os - cillator requiring no external components. the internal rc oscillator has three fixed frequencies of either 4mhz, 8mhz or 12mhz selected by configuration op- tions. device trimming during the manufacturing pro- cess and the inclusion of internal frequency compensation circuits are used to ensure that the influ- ence of the power supply voltage, temperature and pro- cess variations on the oscillation frequency are minimised. as a result, at a power supply of either 3.3v or 5v and at a temperature of 25 c degrees, the fixed oscillation frequency of 4mhz, 8mhz or 12mhz will have a tolerance within 2%. note that if this internal system clock option is selected, as it requires no external pins for its operation, i/o pins pc1 and pc2 are free for use as normal i/o pins. watchdog timer oscillator the wdt oscillator is a fully self-contained free running on-chip rc oscillator with a typical period of 65 sat5v requiring no external components. when the device en - ters the power down mode, the system clock will stop running but the wdt oscillator continues to free-run and to keep the watchdog active. however, to preserve power in certain applications the wdt oscillator can be disabled via a configuration option. / # ? $ ( # # $ $ $ ! + / # ' f c / = ' : $ % = # = $ ! * / # ' ' ' ? $ % 6 ' = crystal/resonator oscillator / # ? b 3 f ' external rc oscillator # / internal rc oscillator -- hirc HT83F02 rev. 1.20 42 november 19, 2010 power down mode and wake-up power down mode all of the holtek microcontrollers have the ability to enter a power down mode, also known as the halt mode or sleep mode. when the device enters this mode, the nor - mal operating current, will be reduced to an extremely low standby current level. this occurs because when the device enters the power down mode, the system oscillator is stopped which reduces the power consump - tion to extremely low levels, however, as the device maintains its present internal condition, it can be woken up at a later stage and continue running, without requir - ing a full reset. this feature is extremely important in ap - plication areas where the mcu must have its power supply constantly maintained to keep the device in a known condition but where the power supply capacity is limited such as in battery applications. entering the power down mode there is only one way for the device to enter the power down mode and that is to execute the halt instruc - tion in the application program. when this instruction is executed, the following will occur: the system oscillator will stop running and the appli - cation program will stop at the halt instruction. the data memory contents and registers will maintain their present condition. the wdt will be cleared and resume counting if the wdt clock source is selected to come from the wdt oscillator. the wdt will stop if its clock source origi- nates from the system clock. the i/o ports will maintain their present condition. in the status register, the power down flag, pdf, will be set and the watchdog time-out flag, to, will be cleared. standby current considerations as the main reason for entering the power down mode is to keep the current consumption of the mcu to as low a value as possible, perhaps only in the order of several micro-amps, there are other considerations which must also be taken into account by the circuit designer if the power consumption is to be minimized. special atten - tion must be made to the i/o pins on the device. all high-impedance input pins must be connected to either a fixed high or low level as any floating input pins could create internal oscillations and result in increased cur - rent consumption. care must also be taken with the loads, which are connected to i/os, which are setup as outputs. these should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other cmos inputs. also note that additional standby current will also be required if the configuration options have enabled the watchdog timer internal oscillator. wake-up after the system enters the power down mode, it can be woken up from one of various sources listed as follows: an external reset an external falling edge on port a a system interrupt a wdt overflow if the system is woken up by an external reset, the de - vice will experience a full system reset, however, if the device is woken up by a wdt overflow, a watchdog timer reset will be initiated. although both of these wake-up methods will initiate a reset operation, the ac - tual source of the wake-up can be determined by exam - ining the to and pdf flags. the pdf flag is cleared by a system power-up or executing the clear watchdog timer instructions and is set when executing the halt instruction. the to flag is set if a wdt time-out occurs, and causes a wake-up that only resets the program counter and stack pointer, the other flags remain in their original status. each pin on port a can be setup via an individual config - uration option to permit a negative transition on the pin to wake-up the system. when a port a pin wake-up oc- curs, the program will resume execution at the instruc- tion following the halt instruction. if the system is woken up by an interrupt, then two possi- ble situations may occur. the first is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume exe- cution at the instruction following the halt instruction. in this situation, the interrupt which woke-up the device will not be immediately serviced, but will rather be ser - viced later when the related interrupt is finally enabled or when a stack level becomes free. the other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. if an interrupt request flag is set to 1 be - fore entering the power down mode, the wake-up func - tion of the related interrupt will be disabled. no matter what the source of the wake-up event is, once a wake-up situation occurs, a time period equal to 1024 system clock periods will be required before normal sys - tem operation resumes. however, if the wake-up has originated due to an interrupt, the actual interrupt sub - routine execution will be delayed by an additional one or more cycles. if the wake-up results in the execution of the next instruction following the halt instruction, this will be executed immediately after the 1024 system clock period delay has ended. HT83F02 rev. 1.20 43 november 19, 2010 low voltage reset lvr the microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device, which is selected via a configuration option. if the supply voltage of the device drops to within a range of 0.9v~vlvr such as might occur when changing the battery, the lvr will automatically reset the device inter - nally. low voltage detector lvd this low voltage detect internal function provides a means for the user to monitor when the power supply voltage falls below a certain fixed level as specified in the dc characteristics. bit 2 of pwmc register and low voltage detector option are used to control the overall function of the lvd. low voltage detector option is the enable/disable control bit, when select disable the over - all function of the lvd will be disabled. bit 2 is the lvd detector output bit and is known as lvdf. under normal operation, and when the power supply voltage is above the specified vlvd value in the dc characteristic section, the lvdf bit will remain at a zero value. if the power supply voltage should fall below this vlvd value then the lvdf bit will change to a high value indicating a low voltage condition. note that the lvdf bit is a read-only bit. by polling the lvdf bit in the pwmc register, the application program can therefore determine the presence of a low voltage condition. operation the low voltage detector must first be enabled using a configuration option. the lvd control bit is bit 2 of the pwmc regsiter and is known as lvdf. under normal operation, and when the power supply voltage is above the specified vlvd value in the dc characteristic section, the lvdf bit will remain at a zero value. if the power supply voltage should fall be - low this vlvd value then the lvdf bit will change to a high value indicating a low voltage condition. note that the lvdf bit is a read-only bit. by polling the lvdf bit in the pwmc register, the application program can there - fore determine the presence of a low voltage condition. watchdog timer the watchdog timer is provided to prevent program malfunctions or sequences from jumping to unknown lo - cations, due to certain uncontrollable external events such as electrical noise. it operates by providing a de - vice reset when the wdt counter overflows. the wdt clock is supplied by one of two sources selected by con - figuration option: its own self-contained dedicated inter - nal wdt oscillator, or the instruction clock which is the system clock divided by 4. note that if the wdt configu - ration option has been disabled, then any instruction re - lating to its operation will result in no operation. the internal wdt oscillator has an approximate period of 65 s at a supply voltage of 5v. if selected, it is first di - vided by 256 via an 8-stage counter to give a nominal period of 17ms. note that this period can vary with vdd, temperature and process variations. for longer wdt time-out periods the wdt prescaler can be utilized. by writing the required value to bits 0, 1 and 2 of the wdts register, known as ws0, ws1 and ws2, longer time-out periods can be achieved. with ws0, ws1 and ws2 all equal to 1, the division ratio is 1:128 which gives a maxi - mum time-out period of about 2.1s. a configuration option can select the instruction clock, which is the system clock divided by 4, as the wdt clock source instead of the internal wdt oscillator. if the in - struction clock is used as the clock source, it must be noted that when the system enters the power down mode, as the system clock is stopped, then the wdt clock source will also be stopped. therefore the wdt will lose its protecting purposes. in such cases the sys - tem cannot be restarted by the wdt and can only be re - started using external signals. for systems that operate in noisy environments, using the internal wdt oscillator is therefore the recommended choice. under normal program operation, a wdt time-out will initialise a device reset and set the status bit to. how- ever, if the system is in the power down mode, when a wdt time-out occurs, only the program counter and stack pointer will be reset. three methods can be adopted to clear the contents of the wdt and the wdt prescaler. the first is an external hardware reset, which means a low level on the res pin, the second is using the watchdog software instructions and the third is via a halt instruction. there are two methods of using software instructions to clear the watchdog timer, one of which must be chosen by configuration option. the first option is to use the sin - gle clr wdt instruction while the second is to use the two commands clr wdt1 and clr wdt2 . for the first option, a simple execution of clr wdt will clear the wdt while for the second option, both clr wdt1 and clr wdt2 must both be executed to successfully clear the wdt. note that for this second option, if clr wdt1 is used to clear the wdt, succes - sive executions of this instruction will have no effect, only the execution of a clr wdt2 instruction will clear the wdt. similarly, after the clr wdt2 instruc - tion has been executed, only a successive clr wdt1 instruction can clear the watchdog timer. HT83F02 rev. 1.00 44 august 31, 2010 voice output the device contains an internal 12-bit dac function which can be used for audio signal generation. voice control two internal registers dal and dah contain the 12-bit digital value for conversion by the internal dac. there is also a dac enable/disable control bit in the pwmc con - trol register for overall on/off control of the dac circuit. if the dac circuit is not enabled, the dah/dal value out - puts will be invalid. writing a 1 to the dac bit in bit1 of pwmc will enable the enable dac circuit, while writing a 0 to the dac bit will disable the dac circuit. audio output and volume control dal, dah, vol the audio output is 12-bits wide whose highest 8-bits are written into the dah register and whose lowest four bits are written into the highest four bits of the dal regis - ter. bits 0~3 of the dal register are always read as zero. there are 8 levels of volume which are setup using the vol register. only the lowest 3-bits of this register are used for volume control. vol[2:0] dac volume control 111 high volume low volume 110 101 100 011 010 001 000 $ - # 4 5 . 6 / & k " $ " 0 m " # " $ " ' ? ! $ ' ) " / ! ) " # ! / # $ ) ) ? b 3 " " $ ? ! $ ' watchdog timer , 6 0 f $ % > % i 0 i 7 # / 0 $ % $ ' $ , , 6 0 / / / 0 9 $ % $ ' $ , 6 0 f $ % > % i 0 i $ % ! ! # ! $ 6 5 4 3 & % " $ ' $ + ) # + ) / + ) 0 " # - , 6 0 " ' " # 0 0 0 0 / / / / " / 0 0 / / 0 0 / / " 0 0 / 0 / 0 / 0 / " / c / / c # / c 3 / c / c / 5 / c 7 # / c 5 3 / c / # f $ % " / " 0 watchdog timer register HT83F02 rev. 1.20 45 november 19, 2010 pulse width modulation output all devices include a single 12-bit pwm function which can directly drive external audio components such as speakers. pulse width modulator operation the pwm output is provided on two complimentary out - puts on the pwm1 and pwm2 pins, providing a differen - tial output pair and thus capable of higher drive power. these two pins can directly drive a piezo buzzer or an 8 ohm speaker without using external components. the pwm outputs can also be used single ended, where the signal is provided on the pwm1 output, and again can also be used by itself alone to drive a piezo buzzer or an 8 ohm speaker without external components. this single end output drive type is chosen using the single_pwm bit in the pwmc register. if the msb_sign bit is low, then the signal that is pro - vided on pwm1and pwm2 will obtain a gnd level volt - age after setting the pwmcc bit high. if the msb_sign bit is high, then the signal that is provided on pwm2 and pwm1 will have a gnd level voltage when the pwmcc bit is set high. the two pwm outputs will initially be at low levels, and if the pwm function is stopped will also return to a low level. if the pwmcc bit changes from low to high then the pwm function will start running and latch new data. if the data is not updated then the old value will remain. if the pwmcc bit changes from high to low, at the end of the duty cycle, the pwm output will stop. v[3:0] pwm volume control 1xxx high volume low volume 0111 0110 0101 0100 0011 0010 0001 0000 - & 0 " f h ) ( 8 " 6 1 8 h f " ( / c 0 c % / c 0 c % ) + % ? ! / c ) + % 0 c ) + % ! " $ ' $ / c ! $ ' $ 0 c % $ $ ' $ f ' % > % i 0 i / / / c / / 0 c / / ) + pulse width modulator control register ' " / " # 0 = 0 / g 0 = 0 / g i g i % $ ! % ! " $ > % ' = f c - & 6 0 f $ % > % i 0 i 7 # / 0 " $ ' $ + $ - . & ! . + $ ! , ! / - & 6 0 / / / 0 9 " $ ' $ + $ - . & ! . + $ ! , 6 0 f $ % > % i 0 i " $ % ! ! # ! $ 6 5 4 3 & % $ % $ ' $ + 0+ /+ #+ 7 HT83F02 rev. 1.20 46 november 19, 2010 configuration options configuration options refer to certain options within the mcu that are programmed into the device during the program - ming process. during the development process, these options are selected using the ht-ide software development tools. as these options are programmed into the device using the hardware programming tools, once they are selected they cannot be changed later by the application software. no. options i/o options 1 pa0~pa7: wake-up enable or disable 2 pa0~pa7: pull-high enable or disable 3 pb0~pb7: pull-high enable or disable oscillator options 4 osc type selection: erc, crystal or hirc hirc options 5 hirc option: 4mhz, 8mhz, 12mhz watchdog options 6 wdt: enable or disable 7 wdt clock source: wdtosc or t1 pb i/o port output voltage options 8 vdd_pbio/vdd type selection: vdd_pbio or vdd for port b, spi, i 2 c i/o per bit lvr option 9 lvr function: enable or disable lvd option 10 lvd function: enable or disable reset options 11 reset function: pc0 or reset pin sima options 12 sima function: enable or disable 13 spia s/w csen: enable or disable 14 spia s/w wcol: enable or disable 15 i 2 ca rnic: enable or disable 16 i 2 ca debounce time: 0/1/2 system clocks simb options 17 simb function: enable or disable 18 spib s/w csen: enable or disable 19 spib s/w wcol: enable or disable 20 i 2 cb rnic: enable or disable 21 i 2 cb debounce time: 0/1/2 system clocks application circuits v dd =2.4v~5.5v HT83F02 rev. 1.20 47 november 19, 2010 vdd1 vd d 1 vd d 2 vd d v33 vd d 1 vdd v33 v33 v33 v33 vdd2 vd d v3 3 v33 vd d v33 sp+ sp- pwm1 pwm2 pb2 au d _ i n sp - vr ef vo l pa2 pa7 pa5 pa1 pa4 pa3 pa0 pa6 pb2 pa3 pa2 pa7 sk pa1 aud vss1 pa5 pa4 pa0 si pa6 pwm2 scsba so vss2 pwm1 si resb sk sc sb a vd d pa 0 pa 2 vs s so pb2 sp+ si so sk si so vs s resb vdd2 vdd1 vd d aud scsba vss1 vss1 sk vss1 vss1 vs s vss vss vs s d1 power led vr1 50k c11 0.0 1u u2 ht 82v 739 1 2 3 4 8 7 6 5 out n audin vref vss vdd outp nc ceb c1 0 0 .1uf c9 10uf c8 100u f jp14 e-w r iter plus con 1 3 5 7 9 11 13 15 17 19 2 4 6 8 10 12 14 16 18 20 1 3 5 7 9 11 13 15 17 19 2 4 6 8 10 12 14 16 18 20 r8 330 d4 play le d r1 1 10 c12 10u c22 0.1u r5 100k ja1 mi ni u s b c on 1 2 3 4 5 vdd usb- usb+ vss vss sw2 2 1 3 5 4 6 u15 mx25 l160 6e (8- sop 2 00m il) 1 2 3 4 8 7 6 5 cs# so wp# gnd vcc hold# sc l k si r10 47k sw 2 4 power switc h 2 1 3 + c1 100u ls 1 speaker c2 0.1u bt1 battery 1 2 d2 1n5 817 r9 330 s3 1 2 r12 0 s4 1 2 s2 1 2 s1 1 2 s6 1 2 s7 1 2 c20 10 u s8 1 2 c2 1 0.1u c3 0.1u sw 9 1 2 u14 mx25 l128 45e (16 -s op 300 mil) 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 nc vcc nc nc nc nc cs# so sclk si nc nc nc nc gnd wp# s5 1 2 r14 47k c23 0.1u c25 0.1u c19 0. 1u sw3 jumper 3 2 u3 ht 7233 2 3 1 vin vout gnd u1 HT83F02(28-ssop 150mil) 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 25 26 27 28 pa 1 pa6 pa 0 pa7 pb 0 vss pb 1 vdd pb 2 vcca3 pb 4 / sd o resb pb 5 / sc l k vssa1 pb 6 / sd i pwm2 pb 7 / sc s b pwm1 osc 1 vcca1 osc 2 vc c a2 vssa2 au d pa5 pa4 pa3 pa2 8-s op ( 150 mil) on of f ke y5 ke y2 ke y3 ke y7 ke y4 ke y6 ke y1 ke y8 r eset po we r cir cu it spi flash connector power amplifier led & key HT83F02 rev. 1.20 48 november 19, 2010 instruction set introduction central to the successful operation of any microcontroller is its instruction set, which is a set of pro - gram instruction codes that directs the microcontroller to perform certain operations. in the case of holtek microcontrollers, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of pro - gramming overheads. for easier understanding of the various instruction codes, they have been subdivided into several func - tional groupings. instruction timing most instructions are implemented within one instruc - tion cycle. the exceptions to this are branch, call, or ta - ble read instructions where two instruction cycles are required. one instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8mhz system oscillator, most instructions would be implemented within 0.5 s and branch or call instructions would be im - plemented within 1 s. although instructions which re - quire one more cycle to implement are generally limited to the jmp, call, ret, reti and table read instruc- tions, it is important to realize that any other instructions which involve manipulation of the program counter low register or pcl will also take one more cycle to imple- ment. as instructions which change the contents of the pcl will imply a direct jump to that new address, one more cycle will be required. examples of such instruc- tions would be clr pcl or mov pcl, a . for the case of skip instructions, it must be noted that if the re- sult of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. moving and transferring data the transfer of data within the microcontroller program is one of the most frequently used operations. making use of three kinds of mov instructions, data can be transferred from registers to the accumulator and vice-versa as well as being able to move specific imme - diate data directly into the accumulator. one of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. arithmetic operations the ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. within the holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. care must be taken to en - sure correct handling of carry and borrow data when re - sults exceed 255 for addition and less than 0 for subtraction. the increment and decrement instructions inc, inca, dec and deca provide a simple means of increasing or decreasing by a value of one of the values in the destination specified. logical and rotate operations the standard logical operations such as and, or, xor and cpl all have their own instruction within the holtek microcontroller instruction set. as with the case of most instructions involving data manipulation, data must pass through the accumulator which may involve additional programming steps. in all logical data operations, the zero flag may be set if the result of the operation is zero. another form of logical data manipulation comes from the rotate instructions such as rr, rl, rrc and rlc which provide a simple means of rotating one bit right or left. different rotate instructions exist depending on pro - gram requirements. rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the carry bit from where it can be examined and the necessary serial bit set high or low. another application where rotate data operations are used is to implement multiplication and division calculations. branches and control transfer program branching takes the form of either jumps to specified locations using the jmp instruction or to a sub- routine using the call instruction. they differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the sub - routine has been carried out. this is done by placing a return instruction ret in the subroutine which will cause the program to jump back to the address right after the call instruction. in the case of a jmp instruction, the program simply jumps to the desired location. there is no requirement to jump back to the original jumping off point as in the case of the call instruction. one special and extremely useful set of branch instructions are the conditional branches. here a decision is first made re - garding the condition of a certain data memory or indi - vidual bits. depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. these instructions are the key to decision making and branching within the pro - gram perhaps determined by the condition of certain in - put switches or by the condition of internal data bits. HT83F02 rev. 1.20 49 november 19, 2010 bit operations the ability to provide single bit operations on data mem - ory is an extremely flexible feature of all holtek microcontrollers. this feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the set [m].i or clr [m].i instructions respectively. the fea - ture removes the need for programmers to first read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. this read-modify-write pro - cess is taken care of automatically when these bit oper - ation instructions are used. table read operations data storage is normally implemented by using regis - ters. however, when working with large amounts of fixed data, the volume involved often makes it inconve - nient to store the fixed data in the data memory. to over - come this problem, holtek microcontrollers allow an area of program memory to be setup as a table where data can be directly stored. a set of easy to use instruc - tions provides the means by which this fixed data can be referenced and retrieved from the program memory. other operations in addition to the above functional instructions, a range of other instructions also exist such as the halt in - struction for power-down operations and instructions to control the operation of the watchdog timer for reliable program operations under extreme electric or electro - magnetic environments. for their relevant operations, refer to the functional related sections. instruction set summary the following table depicts a summary of the instruction set categorised according to function and can be con - sulted as a basic instruction reference using the follow - ing listed conventions. table conventions: x: bits immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address mnemonic description cycles flag affected arithmetic add a,[m] addm a,[m] add a,x adc a,[m] adcm a,[m] sub a,x sub a,[m] subm a,[m] sbc a,[m] sbcm a,[m] daa [m] add data memory to acc add acc to data memory add immediate data to acc add data memory to acc with carry add acc to data memory with carry subtract immediate data from the acc subtract data memory from acc subtract data memory from acc with result in data memory subtract data memory from acc with carry subtract data memory from acc with carry, result in data memory decimal adjust acc for addition with result in data memory 1 1 note 1 1 1 note 1 1 1 note 1 1 note 1 note z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov c logic operation and a,[m] or a,[m] xor a,[m] andm a,[m] orm a,[m] xorm a,[m] and a,x or a,x xor a,x cpl [m] cpla [m] logical and data memory to acc logical or data memory to acc logical xor data memory to acc logical and acc to data memory logical or acc to data memory logical xor acc to data memory logical and immediate data to acc logical or immediate data to acc logical xor immediate data to acc complement data memory complement data memory with result in acc 1 1 1 1 note 1 note 1 note 1 1 1 1 note 1 z z z z z z z z z z z increment & decrement inca [m] inc [m] deca [m] dec [m] increment data memory with result in acc increment data memory decrement data memory with result in acc decrement data memory 1 1 note 1 1 note z z z z HT83F02 rev. 1.20 50 november 19, 2010 mnemonic description cycles flag affected rotate rra [m] rr [m] rrca [m] rrc [m] rla [m] rl [m] rlca [m] rlc [m] rotate data memory right with result in acc rotate data memory right rotate data memory right through carry with result in acc rotate data memory right through carry rotate data memory left with result in acc rotate data memory left rotate data memory left through carry with result in acc rotate data memory left through carry 1 1 note 1 1 note 1 1 note 1 1 note none none c c none none c c data move mov a,[m] mov [m],a mov a,x move data memory to acc move acc to data memory move immediate data to acc 1 1 note 1 none none none bit operation clr [m].i set [m].i clear bit of data memory set bit of data memory 1 note 1 note none none branch jmp addr sz [m] sza [m] sz [m].i snz [m].i siz [m] sdz [m] siza [m] sdza [m] call addr ret ret a,x reti jump unconditionally skip if data memory is zero skip if data memory is zero with data movement to acc skip if bit i of data memory is zero skip if bit i of data memory is not zero skip if increment data memory is zero skip if decrement data memory is zero skip if increment data memory is zero with result in acc skip if decrement data memory is zero with result in acc subroutine call return from subroutine return from subroutine and load immediate data to acc return from interrupt 2 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 2 2 2 2 none none none none none none none none none none none none none table read tabrdc [m] tabrdl [m] read table (current page) to tblh and data memory read table (last page) to tblh and data memory 2 note 2 note none none miscellaneous nop clr [m] set [m] clr wdt clr wdt1 clr wdt2 swap [m] swapa [m] halt no operation clear data memory set data memory clear watchdog timer pre-clear watchdog timer pre-clear watchdog timer swap nibbles of data memory swap nibbles of data memory with result in acc enter power down mode 1 1 note 1 note 1 1 1 1 note 1 1 none none none to, pdf to, pdf to, pdf none none to, pdf note: 1. for skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. any instruction which changes the contents of the pcl will also require 2 cycles for execution. 3. for the clr wdt1 and clr wdt2 instructions the to and pdf flags may be affected by the execution status. the to and pdf flags are cleared after both clr wdt1 and clr wdt2 instructions are consecutively executed. otherwise the to and pdf flags remain unchanged. instruction definition adc a,[m] add data memory to acc with carry description the contents of the specified data memory, accumulator and the carry flag are added. the result is stored in the accumulator. operation acc acc+[m]+c affected flag(s) ov, z, ac, c adcm a,[m] add acc to data memory with carry description the contents of the specified data memory, accumulator and the carry flag are added. the result is stored in the specified data memory. operation [m] acc+[m]+c affected flag(s) ov, z, ac, c add a,[m] add data memory to acc description the contents of the specified data memory and the accumulator are added. the result is stored in the accumulator. operation acc acc + [m] affected flag(s) ov, z, ac, c add a,x add immediate data to acc description the contents of the accumulator and the specified immediate data are added. the result is stored in the accumulator. operation acc acc+x affected flag(s) ov, z, ac, c addm a,[m] add acc to data memory description the contents of the specified data memory and the accumulator are added. the result is stored in the specified data memory. operation [m] acc + [m] affected flag(s) ov, z, ac, c and a,[m] logical and data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical and op - eration. the result is stored in the accumulator. operation acc acc and [m] affected flag(s) z and a,x logical and immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical and operation. the result is stored in the accumulator. operation acc acc and x affected flag(s) z andm a,[m] logical and acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical and op - eration. the result is stored in the data memory. operation [m] acc and [m] affected flag(s) z HT83F02 rev. 1.20 51 november 19, 2010 call addr subroutine call description unconditionally calls a subroutine at the specified address. the program counter then in - crements by 1 to obtain the address of the next instruction which is then pushed onto the stack. the specified address is then loaded and the program continues execution from this new address. as this instruction requires an additional operation, it is a two cycle instruc - tion. operation stack program counter + 1 program counter addr affected flag(s) none clr [m] clear data memory description each bit of the specified data memory is cleared to 0. operation [m] 00h affected flag(s) none clr [m].i clear bit of data memory description bit i of the specified data memory is cleared to 0. operation [m].i 0 affected flag(s) none clr wdt clear watchdog timer description the to, pdf flags and the wdt are all cleared. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf clr wdt1 pre-clear watchdog timer description the to, pdf flags and the wdt are all cleared. note that this instruction works in conjunc- tion with clr wdt2 and must be executed alternately with clr wdt2 to have effect. re- petitively executing this instruction without alternately executing clr wdt2 will have no effect. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf clr wdt2 pre-clear watchdog timer description the to, pdf flags and the wdt are all cleared. note that this instruction works in conjunc - tion with clr wdt1 and must be executed alternately with clr wdt1 to have effect. re - petitively executing this instruction without alternately executing clr wdt1 will have no effect. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf HT83F02 rev. 1.20 52 november 19, 2010 cpl [m] complement data memory description each bit of the specified data memory is logically complemented (1 s complement). bits which previously contained a 1 are changed to 0 and vice versa. operation [m] [m] affected flag(s) z cpla [m] complement data memory with result in acc description each bit of the specified data memory is logically complemented (1 s complement). bits which previously contained a 1 are changed to 0 and vice versa. the complemented result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc [m] affected flag(s) z daa [m] decimal-adjust acc for addition with result in data memory description convert the contents of the accumulator value to a bcd ( binary coded decimal) value re - sulting from the previous addition of two bcd variables. if the low nibble is greater than 9 or if ac flag is set, then a value of 6 will be added to the low nibble. otherwise the low nibble remains unchanged. if the high nibble is greater than 9 or if the c flag is set, then a value of 6 will be added to the high nibble. essentially, the decimal conversion is performed by add - ing 00h, 06h, 60h or 66h depending on the accumulator and flag conditions. only the c flag may be affected by this instruction which indicates that if the original bcd sum is greater than 100, it allows multiple precision decimal addition. operation [m] acc + 00h or [m] acc + 06h or [m] acc + 60h or [m] acc + 66h affected flag(s) c dec [m] decrement data memory description data in the specified data memory is decremented by 1. operation [m] [m] 1 affected flag(s) z deca [m] decrement data memory with result in acc description data in the specified data memory is decremented by 1. the result is stored in the accu - mulator. the contents of the data memory remain unchanged. operation acc [m] 1 affected flag(s) z halt enter power down mode description this instruction stops the program execution and turns off the system clock. the contents of the data memory and registers are retained. the wdt and prescaler are cleared. the power down flag pdf is set and the wdt time-out flag to is cleared. operation to 0 pdf 1 affected flag(s) to, pdf HT83F02 rev. 1.20 53 november 19, 2010 inc [m] increment data memory description data in the specified data memory is incremented by 1. operation [m] [m]+1 affected flag(s) z inca [m] increment data memory with result in acc description data in the specified data memory is incremented by 1. the result is stored in the accumu - lator. the contents of the data memory remain unchanged. operation acc [m]+1 affected flag(s) z jmp addr jump unconditionally description the contents of the program counter are replaced with the specified address. program execution then continues from this new address. as this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. operation program counter addr affected flag(s) none mov a,[m] move data memory to acc description the contents of the specified data memory are copied to the accumulator. operation acc [m] affected flag(s) none mov a,x move immediate data to acc description the immediate data specified is loaded into the accumulator. operation acc x affected flag(s) none mov [m],a move acc to data memory description the contents of the accumulator are copied to the specified data memory. operation [m] acc affected flag(s) none nop no operation description no operation is performed. execution continues with the next instruction. operation no operation affected flag(s) none or a,[m] logical or data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical or oper - ation. the result is stored in the accumulator. operation acc acc or [m] affected flag(s) z HT83F02 rev. 1.20 54 november 19, 2010 or a,x logical or immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical or op - eration. the result is stored in the accumulator. operation acc acc or x affected flag(s) z orm a,[m] logical or acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical or oper - ation. the result is stored in the data memory. operation [m] acc or [m] affected flag(s) z ret return from subroutine description the program counter is restored from the stack. program execution continues at the re - stored address. operation program counter stack affected flag(s) none ret a,x return from subroutine and load immediate data to acc description the program counter is restored from the stack and the accumulator loaded with the specified immediate data. program execution continues at the restored address. operation program counter stack acc x affected flag(s) none reti return from interrupt description the program counter is restored from the stack and the interrupts are re-enabled by set- ting the emi bit. emi is the master interrupt global enable bit. if an interrupt was pending when the reti instruction is executed, the pending interrupt routine will be processed be- fore returning to the main program. operation program counter stack emi 1 affected flag(s) none rl [m] rotate data memory left description the contents of the specified data memory are rotated left by 1 bit with bit 7 rotated into bit 0. operation [m].(i+1) [m].i; (i = 0~6) [m].0 [m].7 affected flag(s) none rla [m] rotate data memory left with result in acc description the contents of the specified data memory are rotated left by 1 bit with bit 7 rotated into bit 0. the rotated result is stored in the accumulator and the contents of the data memory re - main unchanged. operation acc.(i+1) [m].i; (i = 0~6) acc.0 [m].7 affected flag(s) none HT83F02 rev. 1.20 55 november 19, 2010 rlc [m] rotate data memory left through carry description the contents of the specified data memory and the carry flag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry flag is rotated into bit 0. operation [m].(i+1) [m].i; (i = 0~6) [m].0 c c [m].7 affected flag(s) c rlca [m] rotate data memory left through carry with result in acc description data in the specified data memory and the carry flag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry flag is rotated into the bit 0. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.(i+1) [m].i; (i = 0~6) acc.0 c c [m].7 affected flag(s) c rr [m] rotate data memory right description the contents of the specified data memory are rotated right by 1 bit with bit 0 rotated into bit 7. operation [m].i [m].(i+1); (i = 0~6) [m].7 [m].0 affected flag(s) none rra [m] rotate data memory right with result in acc description data in the specified data memory and the carry flag are rotated right by 1 bit with bit 0 ro- tated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i [m].(i+1); (i = 0~6) acc.7 [m].0 affected flag(s) none rrc [m] rotate data memory right through carry description the contents of the specified data memory and the carry flag are rotated right by 1 bit. bit 0 replaces the carry bit and the original carry flag is rotated into bit 7. operation [m].i [m].(i+1); (i = 0~6) [m].7 c c [m].0 affected flag(s) c rrca [m] rotate data memory right through carry with result in acc description data in the specified data memory and the carry flag are rotated right by 1 bit. bit 0 re - places the carry bit and the original carry flag is rotated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i [m].(i+1); (i = 0~6) acc.7 c c [m].0 affected flag(s) c HT83F02 rev. 1.20 56 november 19, 2010 sbc a,[m] subtract data memory from acc with carry description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc [m] c affected flag(s) ov, z, ac, c sbcm a,[m] subtract data memory from acc with carry and result in data memory description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator. the result is stored in the data memory. note that if the re - sult of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation [m] acc [m] c affected flag(s) ov, z, ac, c sdz [m] skip if decrement data memory is 0 description the contents of the specified data memory are first decremented by 1. if the result is 0 the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m] [m] 1 skip if [m] = 0 affected flag(s) none sdza [m] skip if decrement data memory is zero with result in acc description the contents of the specified data memory are first decremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the specified data memory contents remain unchanged. as this requires the insertion of a dummy in- struction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following instruction. operation acc [m] 1 skip if acc = 0 affected flag(s) none set [m] set data memory description each bit of the specified data memory is set to 1. operation [m] ffh affected flag(s) none set [m].i set bit of data memory description bit i of the specified data memory is set to 1. operation [m].i 1 affected flag(s) none HT83F02 rev. 1.20 57 november 19, 2010 siz [m] skip if increment data memory is 0 description the contents of the specified data memory are first incremented by 1. if the result is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m] [m]+1 skip if [m] = 0 affected flag(s) none siza [m] skip if increment data memory is zero with result in acc description the contents of the specified data memory are first incremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the specified data memory contents remain unchanged. as this requires the insertion of a dummy in - struction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc [m]+1 skip if acc = 0 affected flag(s) none snz [m].i skip if bit i of data memory is not 0 description if bit i of the specified data memory is not 0, the following instruction is skipped. as this re - quires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is 0 the program proceeds with the following instruction. operation skip if [m].i 0 affected flag(s) none sub a,[m] subtract data memory from acc description the specified data memory is subtracted from the contents of the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc [m] affected flag(s) ov, z, ac, c subm a,[m] subtract data memory from acc with result in data memory description the specified data memory is subtracted from the contents of the accumulator. the result is stored in the data memory. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation [m] acc [m] affected flag(s) ov, z, ac, c sub a,x subtract immediate data from acc description the immediate data specified by the code is subtracted from the contents of the accumu - lator. the result is stored in the accumulator. note that if the result of subtraction is nega - tive, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc x affected flag(s) ov, z, ac, c HT83F02 rev. 1.20 58 november 19, 2010 swap [m] swap nibbles of data memory description the low-order and high-order nibbles of the specified data memory are interchanged. operation [m].3~[m].0 [m].7 ~ [m].4 affected flag(s) none swapa [m] swap nibbles of data memory with result in acc description the low-order and high-order nibbles of the specified data memory are interchanged. the result is stored in the accumulator. the contents of the data memory remain unchanged. operation acc.3 ~ acc.0 [m].7 ~ [m].4 acc.7 ~ acc.4 [m].3 ~ [m].0 affected flag(s) none sz [m] skip if data memory is 0 description if the contents of the specified data memory is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruc - tion. operation skip if [m] = 0 affected flag(s) none sza [m] skip if data memory is 0 with data movement to acc description the contents of the specified data memory are copied to the accumulator. if the value is zero, the following instruction is skipped. as this requires the insertion of a dummy instruc - tion while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc [m] skip if [m] = 0 affected flag(s) none sz [m].i skip if bit i of data memory is 0 description if bit i of the specified data memory is 0, the following instruction is skipped. as this re- quires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following instruction. operation skip if [m].i = 0 affected flag(s) none tabrdc [m] read table (current page) to tblh and data memory description the low byte of the program code (current page) addressed by the table pointer (tblp) is moved to the specified data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected flag(s) none tabrdl [m] read table (last page) to tblh and data memory description the low byte of the program code (last page) addressed by the table pointer (tblp) is moved to the specified data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected flag(s) none HT83F02 rev. 1.20 59 november 19, 2010 xor a,[m] logical xor data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical xor op - eration. the result is stored in the accumulator. operation acc acc xor [m] affected flag(s) z xorm a,[m] logical xor acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical xor op - eration. the result is stored in the data memory. operation [m] acc xor [m] affected flag(s) z xor a,x logical xor immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical xor operation. the result is stored in the accumulator. operation acc acc xor x affected flag(s) z HT83F02 rev. 1.20 60 november 19, 2010 package information 28-pin ssop (150mil) outline dimensions symbol dimensions in inch min. nom. max. a 0.228 0.244 b 0.150 0.157 c 0.008 0.012 c 0.386 0.394 d 0.054 0.060 e 0.025 f 0.004 0.010 g 0.022 0.028 h 0.007 0.010 08 symbol dimensions in mm min. nom. max. a 5.79 6.20 b 3.81 3.99 c 0.20 0.30 c 9.80 10.01 d 1.37 1.52 e 0.64 f 0.10 0.25 g 0.56 0.71 h 0.18 0.25 08 HT83F02 rev. 1.20 61 november 19, 2010 # / / 4 / 3 1 n h , ( product tape and reel specifications reel dimensions ssop 28s (150mil) symbol description dimensions in mm a reel outer diameter 330.01.0 b reel inner diameter 100.01.5 c spindle hole diameter 13.0 +0.5/-0.2 d key slit width 2.00.5 t1 space between flange 16.8 +0.3/-0.2 t2 reel thickness 22.20.2 HT83F02 rev. 1.20 62 november 19, 2010 1 / # carrier tape dimensions ssop 28s (150mil) symbol description dimensions in mm w carrier tape width 16.00.3 p cavity pitch 8.00.1 e perforation position 1.750.1 f cavity to perforation (width direction) 7.50.1 d perforation diameter 1.55 +0.10/-0.00 d1 cavity hole diameter 1.50 +0.25/-0.00 p0 perforation pitch 4.00.1 p1 cavity to perforation (length direction) 2.00.1 a0 cavity length 6.50.1 b0 cavity width 10.30.1 k0 cavity depth 2.10.1 t carrier tape thickness 0.300.05 c cover tape width 13.30.1 HT83F02 rev. 1.20 63 november 19, 2010 / " / 0 ( 2 0 1 0 0 ' ! ' / % % % = , HT83F02 rev. 1.20 64 november 19, 2010 holtek semiconductor inc. (headquarters) no.3, creation rd. ii, science park, hsinchu, taiwan tel: 886-3-563-1999 fax: 886-3-563-1189 http://www.holtek.com.tw holtek semiconductor inc. (taipei sales office) 4f-2, no. 3-2, yuanqu st., nankang software park, taipei 115, taiwan tel: 886-2-2655-7070 fax: 886-2-2655-7373 fax: 886-2-2655-7383 (international sales hotline) holtek semiconductor inc. (shenzhen sales office) 5f, unit a, productivity building, no.5 gaoxin m 2nd road, nanshan district, shenzhen, china 518057 tel: 86-755-8616-9908, 86-755-8616-9308 fax: 86-755-8616-9722 holtek semiconductor (usa), inc. (north america sales office) 46729 fremont blvd., fremont, ca 94538 tel: 1-510-252-9880 fax: 1-510-252-9885 http://www.holtek.com copyright 2010 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek as - sumes no responsibility arising from the use of the specifications described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. holtek s products are not authorized for use as critical components in life support devices or systems. holtek reserves the right to alter its products without prior notification. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw. |
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